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soc/intel/meteorlake: Fill PCI SSID parameters 

Set SSID UPD to program DID as SSID for all the on board PCIe devices
if SSID is not being overridden by CONFIG option or device tree.

BUG=b:263846223
TEST=Verify that SSID for all PCI devices is same as their respective
DIDs.

Output of lspci in the OS:
00:00.0 0600: 8086:7d02 (rev 01)
        Subsystem: 8086:7d02
00:02.0 0300: 8086:7d45 (prog-if 00 [VGA controller])
        Subsystem: 8086:7d45
00:04.0 1180: 8086:7d03 (rev 01)
        Subsystem: 8086:7d03
00:05.0 0480: 8086:7d19 (rev 01)
        Subsystem: 8086:7d19
00:06.0 0604: 8086:7e4d (rev 01) (prog-if 00 [Normal decode])
        Subsystem: 8086:7e4d
        Capabilities: [98] Subsystem: 8086:7e4d
00:07.0 0604: 8086:7ec4 (prog-if 00 [Normal decode])
        Subsystem: 8086:7ec4
        Capabilities: [90] Subsystem: 8086:7ec4
00:07.2 0604: 8086:7ec6 (prog-if 00 [Normal decode])
        Subsystem: 8086:7ec6
        Capabilities: [90] Subsystem: 8086:7ec6
00:0a.0 1180: 8086:7d0d (rev 01)
        Subsystem: 8086:7d0d
00:0d.0 0c03: 8086:7ec0 (prog-if 30 [XHCI])
        Subsystem: 8086:7ec0
00:0d.2 0c03: 8086:7ec2 (prog-if 40)
        Subsystem: 8086:7ec2
00:0d.3 0c03: 8086:7ec3 (prog-if 40)
        Subsystem: 8086:7ec3
00:14.0 0c03: 8086:7e7d (rev 01) (prog-if 30 [XHCI])
        Subsystem: 8086:7e7d
00:14.2 0500: 8086:7e7f (rev 01)
        Subsystem: 8086:7e7f
00:14.3 0280: 8086:7e40 (rev 01)
        Subsystem: 8086:0094
00:15.0 0c80: 8086:7e78 (rev 01)
        Subsystem: 8086:7e78
00:15.1 0c80: 8086:7e79 (rev 01)
        Subsystem: 8086:7e79
00:15.3 0c80: 8086:7e7b (rev 01)
        Subsystem: 8086:7e7b
00:16.0 0780: 8086:7e70 (rev 01)
        Subsystem: 8086:7e70
00:19.0 0c80: 8086:7e50 (rev 01)
        Subsystem: 8086:7e50
00:19.1 0c80: 8086:7e51 (rev 01)
        Subsystem: 8086:7e51
00:1c.0 0604: 8086:7e3e (rev 01) (prog-if 00 [Normal decode])
        Subsystem: 8086:7e3e
        Capabilities: [98] Subsystem: 8086:7e3e
00:1e.0 0780: 8086:7e25 (rev 01)
        Subsystem: 8086:7e25
00:1e.3 0c80: 8086:7e30 (rev 01)
        Subsystem: 8086:7e30
00:1f.0 0601: 8086:7e04 (rev 01)
        Subsystem: 8086:7e04
00:1f.3 0401: 8086:7e28 (rev 01)
00:1f.5 0c80: 8086:7e23 (rev 01)
        Subsystem: 8086:7e23

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I364c2052984b6f562bffe8f5ad7035c8b659d369
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Kapil Porwal 2023-01-04 00:54:42 +05:30 committed by Felix Held
parent 14e215b241
commit fbe044235b
1 changed files with 67 additions and 0 deletions
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67
src/soc/intel/meteorlake/fsp_params.c
View File

@ -42,6 +42,8 @@
#define DEF_DMVAL 15
#define DEF_DITOVAL 625
#define MAX_ONBOARD_PCIE_DEVICES 256
static const struct slot_irq_constraints irq_constraints[] = {
{
.slot = PCI_DEV_SLOT_PCIE_3,
@ -701,6 +703,70 @@ static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg)
fsp_debug_event_handler;
}
static void evaluate_ssid(const struct device *dev, uint16_t *svid, uint16_t *ssid)
{
if (!(dev && svid && ssid))
return;
*svid = CONFIG_SUBSYSTEM_VENDOR_ID ? : (dev->subsystem_vendor ? : 0x8086);
*ssid = CONFIG_SUBSYSTEM_DEVICE_ID ? : (dev->subsystem_device ? : 0xfffe);
}
/*
* Programming SSID before FSP-S is important because SSID registers of a few PCIE
* devices (e.g. IPU, Crashlog, XHCI, TCSS_XHCI etc.) are locked after FSP-S hence
* provide a custom SSID (same as DID by default) value via UPD.
*/
static void fill_fsps_pci_ssid_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_meteorlake_config *config)
{
struct svid_ssid_init_entry {
union {
struct {
uint64_t reg:12;
uint64_t function:3;
uint64_t device:5;
uint64_t bus:8;
uint64_t ignore1:4;
uint64_t segment:16;
uint64_t ignore2:16;
};
uint64_t data;
};
struct {
uint16_t svid;
uint16_t ssid;
};
uint32_t ignore3;
};
static struct svid_ssid_init_entry ssid_table[MAX_ONBOARD_PCIE_DEVICES];
const struct device *dev;
int i = 0;
for (dev = all_devices; dev; dev = dev->next) {
if (!(is_dev_enabled(dev) && dev->path.type == DEVICE_PATH_PCI &&
dev->bus->secondary == 0))
continue;
if (dev->path.pci.devfn == PCI_DEVFN_ROOT) {
evaluate_ssid(dev, &s_cfg->SiCustomizedSvid, &s_cfg->SiCustomizedSsid);
} else {
ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID;
ssid_table[i].device = PCI_SLOT(dev->path.pci.devfn);
ssid_table[i].function = PCI_FUNC(dev->path.pci.devfn);
evaluate_ssid(dev, &ssid_table[i].svid, &ssid_table[i].ssid);
i++;
}
}
s_cfg->SiSsidTablePtr = (uintptr_t)ssid_table;
s_cfg->SiNumberOfSsidTableEntry = i;
/* Ensure FSP will program the registers */
s_cfg->SiSkipSsidProgramming = 0;
}
static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
struct soc_intel_meteorlake_config *config)
{
@ -730,6 +796,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
fill_fsps_ufs_params,
fill_fsps_ai_params,
fill_fsps_irq_params,
fill_fsps_pci_ssid_params,
};
for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)