src/soc/intel: Add new device IDs to support coffeelake
1. Add new device IDs for SATA, GT and Northbridge to pci_ids.h 2. Add entry to identify CFL U GT and CPU to respective files 3. Add entry to identify CFL U to report_platform.c BUG=none BRANCH=none TEST=Boot to CFL U RVP board with this patch and check if coreboot is able to enumerate various devices and display correct component names properly in serial logs. Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed Signed-off-by: Maulik <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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@ -2774,6 +2774,8 @@
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#define PCI_DEVICE_ID_INTEL_CNL_SATA 0x9dd5
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#define PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA 0x9dd7
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#define PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA 0x282a
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#define PCI_DEVICE_ID_INTEL_CNP_H_SATA 0xa352
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#define PCI_DEVICE_ID_INTEL_CNP_LP_SATA 0x9dd3
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/* Intel PMC device Ids */
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#define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21
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@ -2882,6 +2884,7 @@
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#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2 0x5A5A
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#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3 0x5A42
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#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4 0x5A4A
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#define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5
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/* Intel Northbridge Ids */
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#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
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@ -2900,6 +2903,7 @@
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#define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04
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#define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02
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#define PCI_DEVICE_ID_INTEL_WHL_ID_W 0x3E34
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#define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0
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/* Intel SMBUS device Ids */
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#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23
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@ -36,7 +36,8 @@ static struct {
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{ CPUID_CANNONLAKE_B0, "Cannonlake B0" },
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{ CPUID_CANNONLAKE_C0, "Cannonlake C0" },
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{ CPUID_CANNONLAKE_D0, "Cannonlake D0" },
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{ CPUID_WHISKEYLAKE_W0, "Whiskeylake W0" },
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{ CPUID_COFFEELAKE_D0, "Coffeelake D0" },
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{ CPUID_WHISKEYLAKE_W0, "Whiskeylake W0"},
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};
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static struct {
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@ -45,7 +46,8 @@ static struct {
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} mch_table[] = {
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{ PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" },
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{ PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" },
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{ PCI_DEVICE_ID_INTEL_WHL_ID_W, "Whiskeylake" },
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{ PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)"},
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{ PCI_DEVICE_ID_INTEL_WHL_ID_W, "Whiskeylake"},
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};
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static struct {
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@ -69,7 +71,8 @@ static struct {
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{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2, "Cannonlake ULT GT1.5" },
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{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, "Cannonlake ULT GT1" },
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{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },
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{ PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT1" },
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{ PCI_DEVICE_ID_INTEL_CFL_GT2_ULT, "Coffeelake ULT GT2"},
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{ PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT1"},
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};
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static uint8_t get_dev_revision(pci_devfn_t dev)
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@ -72,6 +72,8 @@ static const struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_INTEL, CPUID_GLK_A0 },
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{ X86_VENDOR_INTEL, CPUID_GLK_B0 },
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{ X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 },
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{ X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 },
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{ X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 },
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{ 0, 0 },
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};
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@ -38,6 +38,8 @@
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#define CPUID_GLK_A0 0x706a0
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#define CPUID_GLK_B0 0x706a1
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#define CPUID_WHISKEYLAKE_W0 0x806eb
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#define CPUID_COFFEELAKE_D0 0x806ea
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#define CPUID_COFFEELAKE_U0 0x906ea
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/*
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* MP Init callback function to Find CPU Topology. This function is common
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@ -76,6 +76,8 @@ static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_CNL_SATA,
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PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA,
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PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA,
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PCI_DEVICE_ID_INTEL_CNP_H_SATA,
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PCI_DEVICE_ID_INTEL_CNP_LP_SATA,
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0
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};
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@ -302,6 +302,7 @@ static const unsigned short systemagent_ids[] = {
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PCI_DEVICE_ID_INTEL_KBL_ID_H,
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PCI_DEVICE_ID_INTEL_KBL_U_R,
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PCI_DEVICE_ID_INTEL_KBL_ID_DT,
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PCI_DEVICE_ID_INTEL_CFL_ID_U,
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0
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};
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