src/soc/intel: Add new device IDs to support coffeelake

1. Add new device IDs for SATA, GT and Northbridge to pci_ids.h
2. Add entry to identify CFL U GT and CPU to respective files
3. Add entry to identify CFL U to report_platform.c

BUG=none
BRANCH=none
TEST=Boot to CFL U RVP board with this patch and check if coreboot is
able to enumerate various devices and display correct component names properly
in serial logs.

Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed
Signed-off-by: Maulik <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

src/include/device/pci_ids.h

@@ -2774,6 +2774,8 @@
 #define PCI_DEVICE_ID_INTEL_CNL_SATA		0x9dd5
 #define PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA	0x9dd7
 #define PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA	0x282a
+#define PCI_DEVICE_ID_INTEL_CNP_H_SATA		0xa352
+#define PCI_DEVICE_ID_INTEL_CNP_LP_SATA		0x9dd3
 
 /* Intel PMC device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC		0x9d21
@@ -2882,6 +2884,7 @@
 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2		0x5A5A
 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3		0x5A42
 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4		0x5A4A
+#define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT			0x3EA5
 
 /* Intel Northbridge Ids */
 #define PCI_DEVICE_ID_INTEL_APL_NB	0x5af0
@@ -2900,6 +2903,7 @@
 #define PCI_DEVICE_ID_INTEL_CNL_ID_U	0x5A04
 #define PCI_DEVICE_ID_INTEL_CNL_ID_Y	0x5A02
 #define PCI_DEVICE_ID_INTEL_WHL_ID_W	0x3E34
+#define PCI_DEVICE_ID_INTEL_CFL_ID_U	0x3ED0
 
 /* Intel SMBUS device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS		0x9d23

src/soc/intel/cannonlake/bootblock/report_platform.c

@@ -36,6 +36,7 @@ static struct {
 	{ CPUID_CANNONLAKE_B0, "Cannonlake B0" },
 	{ CPUID_CANNONLAKE_C0, "Cannonlake C0" },
 	{ CPUID_CANNONLAKE_D0, "Cannonlake D0" },
+	{ CPUID_COFFEELAKE_D0, "Coffeelake D0" },
 	{ CPUID_WHISKEYLAKE_W0, "Whiskeylake W0"},
 };
 
@@ -45,6 +46,7 @@ static struct {
 } mch_table[] = {
 	{ PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" },
 	{ PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" },
+	{ PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)"},
 	{ PCI_DEVICE_ID_INTEL_WHL_ID_W, "Whiskeylake"},
 };
 
@@ -69,6 +71,7 @@ static struct {
 	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2, "Cannonlake ULT GT1.5" },
 	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, "Cannonlake ULT GT1" },
 	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },
+	{ PCI_DEVICE_ID_INTEL_CFL_GT2_ULT, "Coffeelake ULT GT2"},
 	{ PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT1"},
 };
 

src/soc/intel/common/block/cpu/mp_init.c

@@ -72,6 +72,8 @@ static const struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_GLK_A0 },
 	{ X86_VENDOR_INTEL, CPUID_GLK_B0 },
 	{ X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 },
+	{ X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 },
+	{ X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 },
 	{ 0, 0 },
 };
 

src/soc/intel/common/block/include/intelblocks/mp_init.h

@@ -38,6 +38,8 @@
 #define CPUID_GLK_A0		0x706a0
 #define CPUID_GLK_B0		0x706a1
 #define CPUID_WHISKEYLAKE_W0	0x806eb
+#define CPUID_COFFEELAKE_D0	0x806ea
+#define CPUID_COFFEELAKE_U0	0x906ea
 
 /*
  * MP Init callback function to Find CPU Topology. This function is common

src/soc/intel/common/block/sata/sata.c

@@ -76,6 +76,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_SATA,
 	PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA,
 	PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA,
+	PCI_DEVICE_ID_INTEL_CNP_H_SATA,
+	PCI_DEVICE_ID_INTEL_CNP_LP_SATA,
 	0
 };
 

src/soc/intel/common/block/systemagent/systemagent.c

@@ -302,6 +302,7 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DEVICE_ID_INTEL_KBL_ID_H,
 	PCI_DEVICE_ID_INTEL_KBL_U_R,
 	PCI_DEVICE_ID_INTEL_KBL_ID_DT,
+	PCI_DEVICE_ID_INTEL_CFL_ID_U,
 	0
 };