intel/fsp_baytrail: add Gold3 FSP support
Baytrail Gold3 FSP adds a couple of parameters in UPD_DATA_REGION making platform more configurable via devicetree.cb Update the UPD_DATA_REGION structure and pass settings to FSP Add Baytrail Gold2 and earlier FSP backward compatible, as Gold3 FSP changes UPD_DATA_REGION struct Change-Id: Ia2d2d0595328ac771762a84da40697a3b7e900c6 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/7334 Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)
This commit is contained in:
York Yang
Martin Roth
parent
3fb8b0d75b
commit
fc1c1b572f
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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* Copyright (C) 2014 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -172,6 +173,109 @@ struct soc_intel_fsp_baytrail_config {
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#define LPE_ACPI_MODE_DISABLED 1
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#define LPE_ACPI_MODE_ENABLED 2
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uint32_t SerialDebugPortAddress;
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#define SerialDebugPortAddress_DEFAULT 0
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uint8_t SerialDebugPortType;
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#define SERIAL_DEBUG_PORT_DEFAULT 0
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#define SERIAL_DEBUG_PORT_TYPE_NONE 1
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#define SERIAL_DEBUG_PORT_TYPE_IO 2
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#define SERIAL_DEBUG_PORT_TYPE_MMIO 3
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uint8_t PcdMrcDebugMsg;
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#define MRC_DEBUG_MSG_DEFAULT 0
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#define MRC_DEBUG_MSG_DISABLE 1
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#define MRC_DEBUG_MSG_ENABLE 2
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uint8_t PcdSccEnablePciMode;
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#define SCC_PCI_MODE_DEFAULT 0
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#define SCC_PCI_MODE_DISABLE 1
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#define SCC_PCI_MODE_ENABLE 2
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uint8_t IgdRenderStandby;
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#define IGD_RENDER_STANDBY_DEFAULT 0
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#define IGD_RENDER_STANDBY_DISABLE 1
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#define IGD_RENDER_STANDBY_ENABLE 2
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uint8_t TxeUmaEnable;
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#define TXE_UMA_DEFAULT 0
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#define TXE_UMA_DISABLE 1
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#define TXE_UMA_ENABLE 2
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/* Memory down data */
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uint8_t EnableMemoryDown;
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#define MEMORY_DOWN_DEFAULT 0
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#define MEMORY_DOWN_DISABLE 1
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#define MEMORY_DOWN_ENABLE 2
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uint8_t DRAMSpeed;
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#define DRAM_SPEED_DEFAULT 0
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#define DRAM_SPEED_800MHZ 1
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#define DRAM_SPEED_1066MHZ 2
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#define DRAM_SPEED_1333MHZ 3
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#define DRAM_SPEED_1600MHZ 4
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uint8_t DRAMType;
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#define DRAM_TYPE_DEFAULT 0
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#define DRAM_TYPE_DDR3 1
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#define DRAM_TYPE_DDR3L 2
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uint8_t DIMM0Enable;
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#define DIMM0_ENABLE_DEFAULT 0
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#define DIMM0_DISABLE 1
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#define DIMM0_ENABLE 2
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uint8_t DIMM1Enable;
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#define DIMM1_ENABLE_DEFAULT 0
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#define DIMM1_DISABLE 1
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#define DIMM1_ENABLE 2
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uint8_t DIMMDWidth;
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#define DIMM_DWIDTH_DEFAULT 0
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#define DIMM_DWIDTH_X8 1
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#define DIMM_DWIDTH_X16 2
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#define DIMM_DWIDTH_X32 3
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uint8_t DIMMDensity;
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#define DIMM_DENSITY_DEFAULT 0
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#define DIMM_DENSITY_1G_BIT 1
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#define DIMM_DENSITY_2G_BIT 2
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#define DIMM_DENSITY_4G_BIT 3
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#define DIMM_DENSITY_8G_BIT 4
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uint8_t DIMMBusWidth;
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#define DIMM_BUS_WIDTH_DEFAULT 0
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#define DIMM_BUS_WIDTH_8BIT 1
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#define DIMM_BUS_WIDTH_16BIT 2
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#define DIMM_BUS_WIDTH_32BIT 3
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#define DIMM_BUS_WIDTH_64BIT 4
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uint8_t DIMMSides;
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#define DIMM_SIDES_DEFAULT 0
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#define DIMM_SIDES_1RANK 1
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#define DIMM_SIDES_2RANK 2
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uint8_t DIMMtCL;
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#define DIMM_TCL_DEFAULT 0
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uint8_t DIMMtRPtRCD;
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#define DIMM_TRP_TRCD_DEFAULT 0
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uint8_t DIMMtWR;
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#define DIMM_TWR_DEFAULT 0
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uint8_t DIMMtWTR;
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#define DIMM_TWTR_DEFAULT 0
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uint8_t DIMMtRRD;
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#define DIMM_TRRD_DEFAULT 0
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uint8_t DIMMtRTP;
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#define DIMM_TRTP_DEFAULT 0
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uint8_t DIMMtFAW;
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#define DIMM_TFAW_DEFAULT 0
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/* ***** ACPI configuration ***** */
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/* Options for these are in src/arch/x86/include/arch/acpi.h */
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uint8_t fadt_pm_profile;
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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* Copyright (C) 2014 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -69,7 +70,7 @@ typedef struct soc_intel_fsp_baytrail_config config_t;
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*
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* @param UpdData Pointer to the UPD Data structure
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*/
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static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
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static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData)
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{
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ROMSTAGE_CONST struct device *dev;
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ROMSTAGE_CONST config_t *config;
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@ -146,7 +147,15 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
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switch (dev->path.pci.devfn) {
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case MIPI_DEV_FUNC: /* Camera / Image Signal Processing */
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UpdData->ISPEnable = dev->enabled;
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if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) {
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UpdData->ISPEnable = dev->enabled;
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} else {
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/* Gold2 and earlier FSP: ISPEnable is the filed */
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/* next to PcdGttSize in UPD_DATA_REGION struct */
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*(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled;
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printk (BIOS_DEBUG,
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"Baytrail Gold2 or earlier FSP, adjust ISPEnable offset.\n");
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}
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printk(BIOS_DEBUG, "MIPI/ISP:\t\t%s\n",
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UpdData->PcdEnableSdio?"Enabled":"Disabled");
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break;
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@ -303,6 +312,120 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
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printk(BIOS_DEBUG, "Xhci:\t\t\t%s\n",
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UpdData->PcdEnableXhci?"Enabled":"Disabled");
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if (config->SerialDebugPortAddress != SerialDebugPortAddress_DEFAULT) {
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UpdData->SerialDebugPortAddress = config->SerialDebugPortAddress;
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}
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if (config->SerialDebugPortType != SERIAL_DEBUG_PORT_DEFAULT) {
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UpdData->SerialDebugPortType
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= config->SerialDebugPortType - SERIAL_DEBUG_PORT_TYPE_NONE;
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}
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if (config->PcdMrcDebugMsg != MRC_DEBUG_MSG_DEFAULT) {
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UpdData->PcdMrcDebugMsg
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= config->PcdMrcDebugMsg - MRC_DEBUG_MSG_DISABLE;
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printk (BIOS_DEBUG, "MRC Debug Message:\t%s\n",
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(UpdData->PcdMrcDebugMsg) ? "Enabled" : "Disabled");
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}
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if (config->PcdSccEnablePciMode != SCC_PCI_MODE_DEFAULT) {
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UpdData->PcdSccEnablePciMode
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= config->PcdSccEnablePciMode - SCC_PCI_MODE_DISABLE;
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}
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if (config->IgdRenderStandby != IGD_RENDER_STANDBY_DEFAULT) {
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UpdData->IgdRenderStandby
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= config->IgdRenderStandby - IGD_RENDER_STANDBY_DISABLE;
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printk (BIOS_DEBUG, "IGD Render Standby:\t%s\n",
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(UpdData->IgdRenderStandby) ? "Enabled" : "Disabled");
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}
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if (config->TxeUmaEnable != TXE_UMA_DEFAULT) {
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UpdData->TxeUmaEnable = config->TxeUmaEnable - TXE_UMA_DISABLE;
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}
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/* set memory down parameters */
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if (config->EnableMemoryDown != MEMORY_DOWN_DEFAULT) {
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UpdData->PcdMemoryParameters.EnableMemoryDown
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= config->EnableMemoryDown - MEMORY_DOWN_DISABLE;
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if (config->DRAMSpeed != DRAM_SPEED_DEFAULT) {
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UpdData->PcdMemoryParameters.DRAMSpeed
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= config->DRAMSpeed - DRAM_SPEED_800MHZ;
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}
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if (config->DRAMType != DRAM_TYPE_DEFAULT) {
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UpdData->PcdMemoryParameters.DRAMType
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= config->DRAMType - DRAM_TYPE_DDR3;
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}
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if (config->DIMM0Enable != DIMM0_ENABLE_DEFAULT) {
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UpdData->PcdMemoryParameters.DIMM0Enable
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= config->DIMM0Enable - DIMM0_DISABLE;
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}
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if (config->DIMM1Enable != DIMM1_ENABLE_DEFAULT) {
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UpdData->PcdMemoryParameters.DIMM1Enable
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= config->DIMM1Enable - DIMM1_DISABLE;
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}
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if (config->DIMMDWidth != DIMM_DWIDTH_DEFAULT) {
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UpdData->PcdMemoryParameters.DIMMDWidth
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= config->DIMMDWidth - DIMM_DWIDTH_X8;
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}
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if (config->DIMMDensity != DIMM_DENSITY_DEFAULT) {
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UpdData->PcdMemoryParameters.DIMMDensity
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= config->DIMMDensity - DIMM_DENSITY_1G_BIT;
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}
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if (config->DIMMBusWidth != DIMM_BUS_WIDTH_DEFAULT) {
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UpdData->PcdMemoryParameters.DIMMBusWidth
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= config->DIMMBusWidth - DIMM_BUS_WIDTH_8BIT;
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}
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if (config->DIMMSides != DIMM_SIDES_DEFAULT) {
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UpdData->PcdMemoryParameters.DIMMSides
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= config->DIMMSides - DIMM_SIDES_1RANK;
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}
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if (config->DIMMtCL != DIMM_TCL_DEFAULT)
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UpdData->PcdMemoryParameters.DIMMtCL = config->DIMMtCL;
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if (config->DIMMtRPtRCD != DIMM_TRP_TRCD_DEFAULT)
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UpdData->PcdMemoryParameters.DIMMtRPtRCD = config->DIMMtRPtRCD;
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if (config->DIMMtWR != DIMM_TWR_DEFAULT)
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UpdData->PcdMemoryParameters.DIMMtWR = config->DIMMtWR;
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if (config->DIMMtWTR != DIMM_TWTR_DEFAULT)
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UpdData->PcdMemoryParameters.DIMMtWTR = config->DIMMtWTR;
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if (config->DIMMtRRD != DIMM_TRRD_DEFAULT)
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UpdData->PcdMemoryParameters.DIMMtRRD = config->DIMMtRRD;
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if (config->DIMMtRTP != DIMM_TRTP_DEFAULT)
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UpdData->PcdMemoryParameters.DIMMtRTP = config->DIMMtRTP;
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if (config->DIMMtFAW != DIMM_TFAW_DEFAULT)
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UpdData->PcdMemoryParameters.DIMMtFAW = config->DIMMtFAW;
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printk (BIOS_DEBUG,
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"Memory Down Data Existed : %s\n"\
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"- Speed (0: 800, 1: 1066, 2: 1333, 3: 1600): %d\n"\
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"- Type (0: DDR3, 1: DDR3L) : %d\n"\
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"- DIMM0 : %s\n"\
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"- DIMM1 : %s\n"\
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"- Width : x%d\n"\
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"- Density : %dGbit\n"
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"- BudWidth : %dbit\n"\
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"- Rank # : %d\n"\
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"- tCL : %02X\n"\
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"- tRPtRCD : %02X\n"\
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"- tWR : %02X\n"\
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"- tWTR : %02X\n"\
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"- tRRD : %02X\n"\
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"- tRTP : %02X\n"\
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"- tFAW : %02X\n"
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, (UpdData->PcdMemoryParameters.EnableMemoryDown) ? "Enabled" : "Disabled"
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, UpdData->PcdMemoryParameters.DRAMSpeed
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, UpdData->PcdMemoryParameters.DRAMType
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, (UpdData->PcdMemoryParameters.DIMM0Enable) ? "Enabled" : "Disabled"
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, (UpdData->PcdMemoryParameters.DIMM1Enable) ? "Enabled" : "Disabled"
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, 8 << (UpdData->PcdMemoryParameters.DIMMDWidth)
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, 1 << (UpdData->PcdMemoryParameters.DIMMDensity)
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, 8 << (UpdData->PcdMemoryParameters.DIMMBusWidth)
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, (UpdData->PcdMemoryParameters.DIMMSides) + 1
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, UpdData->PcdMemoryParameters.DIMMtCL
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, UpdData->PcdMemoryParameters.DIMMtRPtRCD
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, UpdData->PcdMemoryParameters.DIMMtWR
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, UpdData->PcdMemoryParameters.DIMMtWTR
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, UpdData->PcdMemoryParameters.DIMMtRRD
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, UpdData->PcdMemoryParameters.DIMMtRTP
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, UpdData->PcdMemoryParameters.DIMMtFAW
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);
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}
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}
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/* Set up the Baytrail specific structures for the call into the FSP */
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@ -318,7 +441,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
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/* Initialize the UPD Data */
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GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr);
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ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr);
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ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr);
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pFspInitParams->NvsBufferPtr = NULL;
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#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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* Copyright (C) 2014 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -46,4 +47,7 @@
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#define FSP_IMAGE_ID_DWORD0 0x56594C56 /* 'VLYV' */
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#define FSP_IMAGE_ID_DWORD1 0x30574549 /* 'IEW0' */
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/* Revision of the FSP binary */
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#define FSP_GOLD3_REV_ID 0x00000303
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#endif /* CHIPSET_FSP_UTIL_H */
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@ -1,6 +1,6 @@
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/**
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Copyright (C) 2013, Intel Corporation
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Copyright (C) 2013-2014 Intel Corporation
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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@ -28,56 +28,78 @@ are permitted provided that the following conditions are met:
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**/
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/**
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This file is auto-generated, please DO NOT modify.
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**/
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#ifndef __VPDHEADER_H__
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#define __VPDHEADER_H__
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#ifndef __FSPVPD_H__
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#define __FSPVPD_H__
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#pragma pack(1)
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typedef struct {
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UINT8 EnableMemoryDown;
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UINT8 DRAMSpeed; /* DRAM Speed */
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UINT8 DRAMType; /* DRAM Type */
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UINT8 DIMM0Enable; /* DIMM 0 Enable */
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UINT8 DIMM1Enable; /* DIMM 1 Enable */
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UINT8 DIMMDWidth; /* DRAM device data width */
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UINT8 DIMMDensity; /* DRAM device data density */
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UINT8 DIMMBusWidth; /* DIMM Bus Width */
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UINT8 DIMMSides; /* Ranks Per DIMM */
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UINT8 DIMMtCL; /* tCL */
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UINT8 DIMMtRPtRCD; /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
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UINT8 DIMMtWR; /* tWR in DRAM clk */
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UINT8 DIMMtWTR; /* tWTR in DRAM clk */
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UINT8 DIMMtRRD; /* tRRD in DRAM clk */
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UINT8 DIMMtRTP; /* tRTP in DRAM clk */
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UINT8 DIMMtFAW; /* tFAW in DRAM clk */
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} MEMORY_DOWN_DATA;
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typedef struct _UPD_DATA_REGION {
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UINT64 Signature; /* Offset 0x0000 */
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UINT32 RESERVED1; /* Offset 0x0008 */
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UINT8 Padding0[20]; /* Offset 0x000C */
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UINT16 PcdMrcInitTsegSize; /* Offset 0x0014 */
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UINT16 PcdMrcInitMmioSize; /* Offset 0x0016 */
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UINT8 PcdMrcInitSPDAddr1; /* Offset 0x0018 */
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UINT8 PcdMrcInitSPDAddr2; /* Offset 0x0019 */
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UINT8 PcdeMMCBootMode; /* Offset 0x001B */
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UINT8 PcdEnableSdio; /* Offset 0x001C */
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UINT8 PcdEnableSdcard; /* Offset 0x001D */
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UINT8 PcdEnableHsuart0; /* Offset 0x001E */
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UINT8 PcdEnableHsuart1; /* Offset 0x001F */
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UINT8 PcdEnableSpi; /* Offset 0x0020 */
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UINT8 PcdEnableLan; /* Offset 0x0021 */
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UINT8 PcdEnableSata; /* Offset 0x0023 */
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UINT8 PcdSataMode; /* Offset 0x002E */
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UINT8 PcdEnableAzalia; /* Offset 0x002F */
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UINT32 AzaliaConfigPtr; /* Offset 0x0030 */
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UINT8 PcdEnableXhci; /* Offset 0x0034 */
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UINT8 PcdEnableLpe; /* Offset 0x0029 */
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UINT8 PcdLpssSioEnablePciMode; /* Offset 0x002A */
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UINT8 PcdEnableDma0; /* Offset 0x002B */
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UINT8 PcdEnableDma1; /* Offset 0x002C */
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UINT8 PcdEnableI2C0; /* Offset 0x002D */
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UINT8 PcdEnableI2C1; /* Offset 0x002E */
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UINT8 PcdEnableI2C2; /* Offset 0x002F */
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UINT8 PcdEnableI2C3; /* Offset 0x0030 */
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UINT8 PcdEnableI2C4; /* Offset 0x0031 */
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UINT8 PcdEnableI2C5; /* Offset 0x0032 */
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UINT8 PcdEnableI2C6; /* Offset 0x0033 */
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UINT8 PcdEnablePwm0; /* Offset 0x0034 */
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UINT8 PcdEnablePwm1; /* Offset 0x0035 */
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UINT8 PcdEnableHsi; /* Offset 0x0036 */
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UINT8 PcdIgdDvmt50PreAlloc; /* Offset 0x0043 */
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UINT8 PcdApertureSize; /* Offset 0x0044 */
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UINT8 PcdGttSize; /* Offset 0x0045 */
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UINT8 ISPEnable; /* Offset 0x0046 */
|
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UINT16 PcdRegionTerminator; /* Offset 0x0047 */
|
||||
UINT64 Signature; /* Offset 0x0000 */
|
||||
UINT32 RESERVED1; /* Offset 0x0008 */
|
||||
UINT8 Padding0[20]; /* Offset 0x000C */
|
||||
UINT16 PcdMrcInitTsegSize; /* Offset 0x0020 */
|
||||
UINT16 PcdMrcInitMmioSize; /* Offset 0x0022 */
|
||||
UINT8 PcdMrcInitSPDAddr1; /* Offset 0x0024 */
|
||||
UINT8 PcdMrcInitSPDAddr2; /* Offset 0x0025 */
|
||||
UINT8 PcdeMMCBootMode; /* Offset 0x0026 */
|
||||
UINT8 PcdEnableSdio; /* Offset 0x0027 */
|
||||
UINT8 PcdEnableSdcard; /* Offset 0x0028 */
|
||||
UINT8 PcdEnableHsuart0; /* Offset 0x0029 */
|
||||
UINT8 PcdEnableHsuart1; /* Offset 0x002A */
|
||||
UINT8 PcdEnableSpi; /* Offset 0x002B */
|
||||
UINT8 PcdEnableLan; /* Offset 0x002C */
|
||||
UINT8 PcdEnableSata; /* Offset 0x002D */
|
||||
UINT8 PcdSataMode; /* Offset 0x002E */
|
||||
UINT8 PcdEnableAzalia; /* Offset 0x002F */
|
||||
UINT32 AzaliaConfigPtr; /* Offset 0x0030 */
|
||||
UINT8 PcdEnableXhci; /* Offset 0x0034 */
|
||||
UINT8 PcdEnableLpe; /* Offset 0x0035 */
|
||||
UINT8 PcdLpssSioEnablePciMode; /* Offset 0x0036 */
|
||||
UINT8 PcdEnableDma0; /* Offset 0x0037 */
|
||||
UINT8 PcdEnableDma1; /* Offset 0x0038 */
|
||||
UINT8 PcdEnableI2C0; /* Offset 0x0039 */
|
||||
UINT8 PcdEnableI2C1; /* Offset 0x003A */
|
||||
UINT8 PcdEnableI2C2; /* Offset 0x003B */
|
||||
UINT8 PcdEnableI2C3; /* Offset 0x003C */
|
||||
UINT8 PcdEnableI2C4; /* Offset 0x003D */
|
||||
UINT8 PcdEnableI2C5; /* Offset 0x003E */
|
||||
UINT8 PcdEnableI2C6; /* Offset 0x003F */
|
||||
UINT8 PcdEnablePwm0; /* Offset 0x0040 */
|
||||
UINT8 PcdEnablePwm1; /* Offset 0x0041 */
|
||||
UINT8 PcdEnableHsi; /* Offset 0x0042 */
|
||||
UINT8 PcdIgdDvmt50PreAlloc; /* Offset 0x0043 */
|
||||
UINT8 PcdApertureSize; /* Offset 0x0044 */
|
||||
UINT8 PcdGttSize; /* Offset 0x0045 */
|
||||
UINT32 SerialDebugPortAddress; /* Offset 0x0046 */
|
||||
UINT8 SerialDebugPortType; /* Offset 0x004A */
|
||||
UINT8 PcdMrcDebugMsg; /* Offset 0x004B */
|
||||
UINT8 ISPEnable; /* Offset 0x004C */
|
||||
UINT8 PcdSccEnablePciMode; /* Offset 0x004D */
|
||||
UINT8 IgdRenderStandby; /* Offset 0x004E */
|
||||
UINT8 TxeUmaEnable; /* Offset 0x004F */
|
||||
UINT8 UnusedUpdSpace1[160]; /* Offset 0x0050 */
|
||||
MEMORY_DOWN_DATA PcdMemoryParameters; /* Offset 0x00F0 */
|
||||
UINT16 PcdRegionTerminator; /* Offset 0x0100 */
|
||||
} UPD_DATA_REGION;
|
||||
|
||||
|
||||
|
|
@ -86,7 +108,7 @@ typedef struct _VPD_DATA_REGION {
|
|||
UINT32 PcdImageRevision; /* Offset 0x0008 */
|
||||
UINT32 PcdUpdRegionOffset; /* Offset 0x000C */
|
||||
UINT8 Padding0[16]; /* Offset 0x0010 */
|
||||
UINT32 RESERVED1; /* Offset 0x0020 */
|
||||
UINT32 PcdFspReservedMemoryLength; /* Offset 0x0020 */
|
||||
UINT8 PcdPlatformType; /* Offset 0x0024 */
|
||||
UINT8 PcdEnableSecureBoot; /* Offset 0x0025 */
|
||||
UINT8 PcdMemoryParameters[16]; /* Offset 0x0026 */
|
||||
|
|
|
|||
Loading…
Reference in New Issue