src: Change bare 'unsigned' to 'unsigned int'
This fixes all of the current code in coreboot/src where a bare unsigned is used incorrectly. A follow-on will fix the comments so that we can enable the unsigned lint checker for src/coreboot. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I37f34a95bb1894e70cd9e076d4b81ebac665eaeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/47482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Martin Roth
Patrick Georgi
parent
c6b77d5bf6
commit
fc2047b1f7
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@ -47,35 +47,35 @@ union dimm_flags_ddr2_st {
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* We do not care how these bits are ordered */
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struct {
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/* Module can work at 5.00V */
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unsigned operable_5_00V:1;
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unsigned int operable_5_00V:1;
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/* Module can work at 3.33V */
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unsigned operable_3_33V:1;
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unsigned int operable_3_33V:1;
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/* Module can work at 2.50V */
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unsigned operable_2_50V:1;
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unsigned int operable_2_50V:1;
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/* Module can work at 1.80V - All DIMMS must be 1.8V operable */
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unsigned operable_1_80V:1;
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unsigned int operable_1_80V:1;
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/* Module can work at 1.50V */
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unsigned operable_1_50V:1;
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unsigned int operable_1_50V:1;
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/* Module can work at 1.35V */
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unsigned operable_1_35V:1;
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unsigned int operable_1_35V:1;
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/* Module can work at 1.20V */
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unsigned operable_1_25V:1;
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unsigned int operable_1_25V:1;
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/* Has an 8-bit bus extension, meaning the DIMM supports ECC */
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unsigned is_ecc:1;
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unsigned int is_ecc:1;
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/* Supports weak driver */
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unsigned weak_driver:1;
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unsigned int weak_driver:1;
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/* Supports terminating at 50 Ohm */
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unsigned terminate_50ohms:1;
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unsigned int terminate_50ohms:1;
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/* Partial Array Self Refresh */
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unsigned pasr:1;
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unsigned int pasr:1;
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/* Supports burst length 8 */
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unsigned bl8:1;
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unsigned int bl8:1;
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/* Supports burst length 4 */
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unsigned bl4:1;
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unsigned int bl4:1;
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/* DIMM Package is stack */
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unsigned stacked:1;
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unsigned int stacked:1;
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/* the assembly supports self refresh */
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unsigned self_refresh:1;
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unsigned int self_refresh:1;
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};
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unsigned int raw;
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};
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@ -27,66 +27,66 @@ struct rk3399_ddr_pi_regs {
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union noc_ddrtiminga0 {
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u32 d32;
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struct {
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unsigned acttoact : 6;
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unsigned reserved0 : 2;
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unsigned rdtomiss : 6;
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unsigned reserved1 : 2;
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unsigned wrtomiss : 6;
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unsigned reserved2 : 2;
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unsigned readlatency : 8;
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unsigned int acttoact : 6;
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unsigned int reserved0 : 2;
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unsigned int rdtomiss : 6;
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unsigned int reserved1 : 2;
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unsigned int wrtomiss : 6;
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unsigned int reserved2 : 2;
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unsigned int readlatency : 8;
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} b;
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};
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union noc_ddrtimingb0 {
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u32 d32;
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struct {
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unsigned rdtowr : 5;
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unsigned reserved0 : 3;
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unsigned wrtord : 5;
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unsigned reserved1 : 3;
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unsigned rrd : 4;
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unsigned reserved2 : 4;
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unsigned faw : 6;
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unsigned reserved3 : 2;
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unsigned int rdtowr : 5;
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unsigned int reserved0 : 3;
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unsigned int wrtord : 5;
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unsigned int reserved1 : 3;
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unsigned int rrd : 4;
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unsigned int reserved2 : 4;
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unsigned int faw : 6;
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unsigned int reserved3 : 2;
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} b;
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};
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union noc_ddrtimingc0 {
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u32 d32;
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struct {
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unsigned burstpenalty : 4;
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unsigned reserved0 : 4;
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unsigned wrtomwr : 6;
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unsigned reserved1 : 18;
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unsigned int burstpenalty : 4;
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unsigned int reserved0 : 4;
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unsigned int wrtomwr : 6;
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unsigned int reserved1 : 18;
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} b;
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};
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union noc_devtodev0 {
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u32 d32;
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struct {
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unsigned busrdtord : 3;
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unsigned reserved0 : 1;
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unsigned busrdtowr : 3;
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unsigned reserved1 : 1;
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unsigned buswrtord : 3;
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unsigned reserved2 : 1;
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unsigned buswrtowr : 3;
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unsigned reserved3 : 17;
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unsigned int busrdtord : 3;
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unsigned int reserved0 : 1;
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unsigned int busrdtowr : 3;
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unsigned int reserved1 : 1;
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unsigned int buswrtord : 3;
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unsigned int reserved2 : 1;
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unsigned int buswrtowr : 3;
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unsigned int reserved3 : 17;
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} b;
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};
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union noc_ddrmode {
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u32 d32;
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struct {
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unsigned autoprecharge : 1;
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unsigned bypassfiltering : 1;
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unsigned fawbank : 1;
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unsigned burstsize : 2;
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unsigned mwrsize : 2;
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unsigned reserved2 : 1;
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unsigned forceorder : 8;
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unsigned forceorderstate : 8;
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unsigned reserved3 : 8;
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unsigned int autoprecharge : 1;
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unsigned int bypassfiltering : 1;
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unsigned int fawbank : 1;
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unsigned int burstsize : 2;
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unsigned int mwrsize : 2;
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unsigned int reserved2 : 1;
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unsigned int forceorder : 8;
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unsigned int forceorderstate : 8;
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unsigned int reserved3 : 8;
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} b;
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};
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