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device/ddr2,ddr3: Rename and move a few things 

In order for ddr2.h and ddr3.h to be included in the same file it
cannot have conflicting definitions, therefore rename a few things and
move some things to a common header.

Change-Id: I6056148872076048e055f1d20a60ac31afd7cde6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
This commit is contained in:
Arthur Heymans 2018-02-12 15:12:34 +01:00 committed by Patrick Georgi
parent 13089b008f
commit fc31e44e47
6 changed files with 100 additions and 101 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/device/dram/ddr2.c
View File

@ -38,11 +38,11 @@
* *
* @param type DIMM type. This is byte[20] of the SPD. * @param type DIMM type. This is byte[20] of the SPD.
*/ */
int spd_dimm_is_registered_ddr2(enum spd_dimm_type type) int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type)
{ {
if ((type == SPD_DIMM_TYPE_RDIMM) if ((type == SPD_DDR2_DIMM_TYPE_RDIMM)
|| (type == SPD_DIMM_TYPE_72B_SO_RDIMM) || (type == SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM)
|| (type == SPD_DIMM_TYPE_MINI_RDIMM)) || (type == SPD_DDR2_DIMM_TYPE_MINI_RDIMM))
return 1; return 1;
return 0; return 0;
@ -297,7 +297,7 @@ static void spd_decode_tRCtRFC_time(u8 *spd_40_41_42, u32 *tRC, u32 *tRFC)
* SPD_STATUS_INVALID_FIELD -- A field with an invalid value was * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was
* detected. * detected.
*/ */
int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]) int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
{ {
u8 spd_size, cl, reg8; u8 spd_size, cl, reg8;
u16 eeprom_size; u16 eeprom_size;
@ -582,7 +582,7 @@ int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
} }
printram("\n"); printram("\n");
dimm->dimm_type = spd[20] & SPD_DIMM_TYPE_MASK; dimm->dimm_type = spd[20] & SPD_DDR2_DIMM_TYPE_MASK;
printram(" Dimm type : %x\n", dimm->dimm_type); printram(" Dimm type : %x\n", dimm->dimm_type);
dimm->flags.is_ecc = !!(spd[11] & 0x3); dimm->flags.is_ecc = !!(spd[11] & 0x3);
@ -648,7 +648,7 @@ static void print_us(const char *msg, u32 val)
* *
* @param dimm pointer to already decoded @ref dimm_attr structure * @param dimm pointer to already decoded @ref dimm_attr structure
*/ */
void dram_print_spd_ddr2(const struct dimm_attr_st *dimm) void dram_print_spd_ddr2(const struct dimm_attr_ddr2_st *dimm)
{ {
char buf[32]; char buf[32];
int i; int i;

70
src/include/device/dram/common.h Normal file
View File

@ -0,0 +1,70 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
* Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef DEVICE_DRAM_COMMON_H
#define DEVICE_DRAM_COMMON_H
/**
* \brief Convenience definitions for TCK values
*
* Different values for tCK, representing standard DDR3 frequencies.
* These values are in 1/256 ns units.
* @{
*/
#define NS2MHZ_DIV256 (1000 << 8)
#define TCK_1333MHZ 192
#define TCK_1200MHZ 212
#define TCK_1100MHZ 232
#define TCK_1066MHZ 240
#define TCK_1000MHZ 256
#define TCK_933MHZ 274
#define TCK_900MHZ 284
#define TCK_800MHZ 320
#define TCK_700MHZ 365
#define TCK_666MHZ 384
#define TCK_533MHZ 480
#define TCK_400MHZ 640
#define TCK_333MHZ 768
#define TCK_266MHZ 960
#define TCK_200MHZ 1280
/** @} */
/**
* \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP
*
* Use this macro instead of printk(); for verbose RAM initialization messages.
* When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically
* disabled.
* @{
*/
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)
#else
#define printram(x, ...)
#endif
/** @} */
/** Result of the SPD decoding process */
enum spd_status {
SPD_STATUS_OK = 0,
SPD_STATUS_INVALID,
SPD_STATUS_CRC_ERROR,
SPD_STATUS_INVALID_FIELD,
};
#endif /* DEVICE_DRAM_COMMON_H */

77
src/include/device/dram/ddr2.h
View File

@ -30,55 +30,24 @@
#include <stdint.h> #include <stdint.h>
#include <spd.h> #include <spd.h>
#include <device/dram/common.h>
/**
* \brief Convenience definitions for TCK values
*
* Different values for tCK, representing standard DDR2 frequencies.
* These values are in 1/256 ns units.
* @{
*/
#define TCK_800MHZ 320
#define TCK_700MHZ 365
#define TCK_666MHZ 384
#define TCK_533MHZ 480
#define TCK_400MHZ 640
#define TCK_333MHZ 768
#define TCK_266MHZ 960
#define TCK_200MHZ 1280
/** @} */
/**
* \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP
*
* Use this macro instead of printk(); for verbose RAM initialization messages.
* When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically
* disabled.
* @{
*/
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)
#else
#define printram(x, ...)
#endif
/** @} */
/* /*
* Module type (byte 20, bits 5:0) of SPD * Module type (byte 20, bits 5:0) of SPD
* This definition is specific to DDR2. DDR3 SPDs have a different structure. * This definition is specific to DDR2. DDR3 SPDs have a different structure.
*/ */
enum spd_dimm_type { enum spd_dimm_type_ddr2 {
SPD_DIMM_TYPE_UNDEFINED = 0x00, SPD_DDR2_DIMM_TYPE_UNDEFINED = 0x00,
SPD_DIMM_TYPE_RDIMM = 0x01, SPD_DDR2_DIMM_TYPE_RDIMM = 0x01,
SPD_DIMM_TYPE_UDIMM = 0x02, SPD_DDR2_DIMM_TYPE_UDIMM = 0x02,
SPD_DIMM_TYPE_SO_DIMM = 0x04, SPD_DDR2_DIMM_TYPE_SO_DIMM = 0x04,
SPD_DIMM_TYPE_72B_SO_CDIMM = 0x06, SPD_DDR2_DIMM_TYPE_72B_SO_CDIMM = 0x06,
SPD_DIMM_TYPE_72B_SO_RDIMM = 0x07, SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM = 0x07,
SPD_DIMM_TYPE_MICRO_DIMM = 0x08, SPD_DDR2_DIMM_TYPE_MICRO_DIMM = 0x08,
SPD_DIMM_TYPE_MINI_RDIMM = 0x10, SPD_DDR2_DIMM_TYPE_MINI_RDIMM = 0x10,
SPD_DIMM_TYPE_MINI_UDIMM = 0x20, SPD_DDR2_DIMM_TYPE_MINI_UDIMM = 0x20,
/* Masks to bits 5:0 to give the dimm type */ /* Masks to bits 5:0 to give the dimm type */
SPD_DIMM_TYPE_MASK = 0x3f, SPD_DDR2_DIMM_TYPE_MASK = 0x3f,
}; };
/** /**
@ -86,7 +55,7 @@ enum spd_dimm_type {
* *
* Characteristic flags for the DIMM, as presented by the SPD * Characteristic flags for the DIMM, as presented by the SPD
*/ */
union dimm_flags_st { union dimm_flags_ddr2_st {
/* The whole point of the union/struct construct is to allow us to clear /* The whole point of the union/struct construct is to allow us to clear
* all the bits with one line: flags.raw = 0. * all the bits with one line: flags.raw = 0.
* We do not care how these bits are ordered */ * We do not care how these bits are ordered */
@ -130,9 +99,9 @@ union dimm_flags_st {
* *
* The characteristics of each DIMM, as presented by the SPD * The characteristics of each DIMM, as presented by the SPD
*/ */
struct dimm_attr_st { struct dimm_attr_ddr2_st {
enum spd_memory_type dram_type; enum spd_memory_type dram_type;
enum spd_dimm_type dimm_type; enum spd_dimm_type_ddr2 dimm_type;
/* BCD SPD revision */ /* BCD SPD revision */
u8 rev; u8 rev;
/* Supported CAS mask, bit 0 == CL0 .. bit7 == CL7 */ /* Supported CAS mask, bit 0 == CL0 .. bit7 == CL7 */
@ -144,7 +113,7 @@ struct dimm_attr_st {
* Fields 0 and 1 are unused. */ * Fields 0 and 1 are unused. */
u32 access_time[8]; u32 access_time[8];
/* Flags extracted from SPD */ /* Flags extracted from SPD */
union dimm_flags_st flags; union dimm_flags_ddr2_st flags;
/* Number of banks */ /* Number of banks */
u8 banks; u8 banks;
/* SDRAM width */ /* SDRAM width */
@ -199,23 +168,15 @@ struct dimm_attr_st {
u32 serial; u32 serial;
}; };
/** Result of the SPD decoding process */
enum spd_status {
SPD_STATUS_OK = 0,
SPD_STATUS_INVALID,
SPD_STATUS_CRC_ERROR,
SPD_STATUS_INVALID_FIELD,
};
/** Maximum SPD size supported */ /** Maximum SPD size supported */
#define SPD_SIZE_MAX_DDR2 128 #define SPD_SIZE_MAX_DDR2 128
int spd_dimm_is_registered_ddr2(enum spd_dimm_type type); int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type);
u8 spd_ddr2_calc_checksum(u8 *spd, int len); u8 spd_ddr2_calc_checksum(u8 *spd, int len);
u32 spd_decode_spd_size_ddr2(u8 byte0); u32 spd_decode_spd_size_ddr2(u8 byte0);
u32 spd_decode_eeprom_size_ddr2(u8 byte1); u32 spd_decode_eeprom_size_ddr2(u8 byte1);
int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]); int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]);
void dram_print_spd_ddr2(const struct dimm_attr_st *dimm); void dram_print_spd_ddr2(const struct dimm_attr_ddr2_st *dimm);
void normalize_tck(u32 *tclk); void normalize_tck(u32 *tclk);
u8 spd_get_msbs(u8 c); u8 spd_get_msbs(u8 c);

36
src/include/device/dram/ddr3.h
View File

@ -31,6 +31,8 @@
#include <stdint.h> #include <stdint.h>
#include <spd.h> #include <spd.h>
#include <device/dram/common.h>
/** /**
* Convenience definitions for SPD offsets * Convenience definitions for SPD offsets
@ -45,32 +47,6 @@
#define SPD_DIMM_PART_LEN 18 #define SPD_DIMM_PART_LEN 18
/** @} */ /** @} */
/**
* \brief Convenience definitions for TCK values
*
* Different values for tCK, representing standard DDR3 frequencies.
* These values are in 1/256 ns units.
* @{
*/
#define NS2MHZ_DIV256 (1000 << 8)
#define TCK_1333MHZ 192
#define TCK_1200MHZ 212
#define TCK_1100MHZ 232
#define TCK_1066MHZ 240
#define TCK_1000MHZ 256
#define TCK_933MHZ 274
#define TCK_900MHZ 284
#define TCK_800MHZ 320
#define TCK_700MHZ 365
#define TCK_666MHZ 384
#define TCK_533MHZ 480
#define TCK_400MHZ 640
#define TCK_333MHZ 768
#define TCK_266MHZ 960
#define TCK_200MHZ 1280
/** @} */
/** /**
* \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP
* *
@ -198,14 +174,6 @@ typedef struct dimm_attr_st {
u8 part_number[17]; u8 part_number[17];
} dimm_attr; } dimm_attr;
/** Result of the SPD decoding process */
enum spd_status {
SPD_STATUS_OK = 0,
SPD_STATUS_INVALID,
SPD_STATUS_CRC_ERROR,
SPD_STATUS_INVALID_FIELD,
};
enum ddr3_xmp_profile { enum ddr3_xmp_profile {
DDR3_XMP_PROFILE_1 = 0, DDR3_XMP_PROFILE_1 = 0,
DDR3_XMP_PROFILE_2 = 1, DDR3_XMP_PROFILE_2 = 1,

2
src/northbridge/intel/i945/raminit.c
View File

@ -362,7 +362,7 @@ static void gather_common_timing(struct sys_info *sysinfo,
for (i = 0; i < (2 * DIMM_SOCKETS); i++) { for (i = 0; i < (2 * DIMM_SOCKETS); i++) {
int device = get_dimm_spd_address(sysinfo, i), bytes_read; int device = get_dimm_spd_address(sysinfo, i), bytes_read;
struct dimm_attr_st dimm_info; struct dimm_attr_ddr2_st dimm_info;
/* Initialize the socket information with a sane value */ /* Initialize the socket information with a sane value */
sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;

2
src/northbridge/intel/x4x/raminit.c
View File

@ -119,7 +119,7 @@ static void mchinfo_ddr2(struct sysinfo *s)
static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd, static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
struct abs_timings *saved_timings, struct sysinfo *s) struct abs_timings *saved_timings, struct sysinfo *s)
{ {
struct dimm_attr_st decoded_dimm; struct dimm_attr_ddr2_st decoded_dimm;
int i; int i;
if (spd_decode_ddr2(&decoded_dimm, raw_spd) != SPD_STATUS_OK) { if (spd_decode_ddr2(&decoded_dimm, raw_spd) != SPD_STATUS_OK) {