amd/stoneyridge: Create gnvs entries for AOAC devices
A later patch will leverage AMD's ASL support for handling AOAC devices. This will gather coreboot's device enables from a bitwise field, where each bit corresponds to the register offset used to control each devices. Create an identical structure, and add it to the nvs ASL and global_nvs_t structure. BUG=b:77602074 Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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@ -47,6 +47,25 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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TCRT, 8, // 0x2E - Critical Threshold
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TPSV, 8, // 0x2F - Passive Threshold
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TMAX, 8, // 0x30 - CPU Tj_max
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Offset (0x34), // 0x34 - AOAC Device Enables
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, 5,
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IC0E, 1, // I2C0, 5
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IC1E, 1, // I2C1, 6
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IC2E, 1, // I2C2, 7
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IC3E, 1, // I2C3, 8
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, 2,
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UT0E, 1, // UART0, 11
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UT1E, 1, // UART1, 12
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, 2,
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ST_E, 1, // SATA, 15
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, 2,
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EHCE, 1, // EHCI, 18
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, 4,
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XHCE, 1, // XCHI, 23
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SD_E, 1, // SD, 24
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, 2,
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ESPI, 1, // ESPI, 27
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, 4,
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/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
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Offset (0x100),
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#include <vendorcode/google/chromeos/acpi/gnvs.asl>
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@ -28,6 +28,7 @@
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#include <compiler.h>
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#include <stdint.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <soc/southbridge.h>
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typedef struct global_nvs_t {
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/* Miscellaneous */
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@ -50,7 +51,9 @@ typedef struct global_nvs_t {
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uint8_t tcrt; /* 0x2E - Critical Threshold */
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uint8_t tpsv; /* 0x2F - Passive Threshold */
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uint8_t tmax; /* 0x30 - CPU Tj_max */
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uint8_t unused[207];
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uint8_t pad1[3];
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aoac_devs_t aoac; /* 0x34 - AOAC device enables */
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uint8_t unused[200];
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/* ChromeOS specific (0x100 - 0xfff) */
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chromeos_acpi_t chromeos;
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@ -400,6 +400,27 @@ struct stoneyridge_aoac {
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int status;
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};
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typedef struct aoac_devs {
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unsigned int :5;
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unsigned int ic0e:1; /* 5: I2C0 */
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unsigned int ic1e:1; /* 6: I2C1 */
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unsigned int ic2e:1; /* 7: I2C2 */
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unsigned int ic3e:1; /* 8: I2C3 */
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unsigned int :2;
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unsigned int ut0e:1; /* 11: UART0 */
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unsigned int ut1e:1; /* 12: UART1 */
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unsigned int :2;
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unsigned int st_e:1; /* 15: SATA */
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unsigned int :2;
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unsigned int ehce:1; /* 18: EHCI */
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unsigned int :4;
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unsigned int xhce:1; /* 23: xHCI */
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unsigned int sd_e:1; /* 24: SDIO */
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unsigned int :2;
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unsigned int espi:1; /* 27: ESPI */
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unsigned int :4;
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} __packed aoac_devs_t;
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struct soc_power_reg {
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uint16_t pm1_sts;
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uint16_t pm1_en;
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