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libpayload: provide icache_invalidate_all() on ARM64 

In order to not duplicate the instruction cache invalidation
sequence provide a common routine to perform the necessary
actions. Also, use it in the appropriate places.

BUG=chrome-os-partner:38231
BRANCH=None
TEST=Compiles successfully for smaug and boots kernel

Change-Id: I1d311dbc70bf225f35d60bb10d8d001065322b3a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ab015156713eb7531378edbd1d779522681d529
Original-Change-Id: I8da7002c56139f8f82503484bfd457a7ec20d083
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/263326
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9903
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Furquan Shaikh 2015-03-31 22:50:17 -07:00 committed by Patrick Georgi
parent c769267395
commit fc45f0ba97
2 changed files with 12 additions and 3 deletions
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4
payloads/libpayload/arch/arm64/cache.c
View File

@ -120,7 +120,5 @@ void dcache_invalidate_by_mva(void const *addr, size_t len)
void cache_sync_instructions(void)
{
dcache_clean_all(); /* includes trailing DSB (in assembly) */
iciallu(); /* includes BPIALLU (architecturally) */
dsb();
isb();
icache_invalidate_all(); /* includes leading DSB and trailing ISB */
}

11
payloads/libpayload/include/arm64/arch/cache.h
View File

@ -103,6 +103,17 @@ void cache_sync_instructions(void);
/* tlb invalidate all */
void tlb_invalidate_all(void);
/* Invalidate all of the instruction cache for PE to PoU. */
static inline void icache_invalidate_all(void)
{
__asm__ __volatile__(
"dsb sy\n\t"
"ic iallu\n\t"
"dsb sy\n\t"
"isb\n\t"
: : : "memory");
}
/*
* Generalized setup/init functions
*/