From fc484bf2ae4df9c4ce49610821fe06b9e0a9f3b7 Mon Sep 17 00:00:00 2001 From: EricKY Cheng Date: Wed, 15 Mar 2023 17:25:10 +0800 Subject: [PATCH] mb/google/skyrim/var/winterhold: Update DPTC settings for final version Follow thermal team's request on b/248086651 comment#32. Update the thermal table setting for each mode and the conditions of temperature switching. BUG=b:248086651,b:241180483 TEST=emerge-skyrim coreboot Change-Id: Ibcf6c110029d39bdc6bfaf46c234a4073ee69f30 Signed-off-by: EricKY Cheng Reviewed-on: https://review.coreboot.org/c/coreboot/+/73732 Tested-by: build bot (Jenkins) Reviewed-by: Tim Van Patten --- .../winterhold/include/variant/acpi/dtts.asl | 8 ++-- .../variants/winterhold/overridetree.cb | 46 +++++++++---------- 2 files changed, 27 insertions(+), 27 deletions(-) diff --git a/src/mainboard/google/skyrim/variants/winterhold/include/variant/acpi/dtts.asl b/src/mainboard/google/skyrim/variants/winterhold/include/variant/acpi/dtts.asl index 2ab433748b..5f3f686e1f 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/include/variant/acpi/dtts.asl +++ b/src/mainboard/google/skyrim/variants/winterhold/include/variant/acpi/dtts.asl @@ -30,15 +30,15 @@ Scope (\_SB) // Table A/B If ((\_SB.PRTN == 0) || (\_SB.PRTN == 1)) { // AMB sensor trigger point - // 44C will store 117(0x75) in mapped memory - // 44C=317K, 317-200(offset)=117(0x75) - If (\_SB.PCI0.LPCB.EC0.TIN4 >= 117) { + // 43C will store 116(0x74) in mapped memory + // 43C=316K, 316-200(offset)=116(0x74) + If (\_SB.PCI0.LPCB.EC0.TIN4 >= 116) { \_SB.DTTB() \_SB.PRTN = 1 Return (0) } // AMB sensor release point - If ((\_SB.PCI0.LPCB.EC0.TIN4 <= 113)) { + If ((\_SB.PCI0.LPCB.EC0.TIN4 <= 112)) { \_SB.DDEF() \_SB.PRTN = 0 Return (0) diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 9dbcd0876b..0cf9ba588b 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -37,10 +37,10 @@ chip soc/amd/mendocino register "slow_ppt_time_constant_s" = "5" register "stt_min_limit" = "15000" - register "stt_m1" = "0x18F" - register "stt_m2" = "0x48F" - register "stt_c_apu" = "0xECC5" - register "stt_skin_temp_apu" = "0x3200" + register "stt_m1" = "0xAE" + register "stt_m2" = "0xB8F" + register "stt_c_apu" = "0xC13B" + register "stt_skin_temp_apu" = "0x3000" # Set Dynamic DPTC thermal profile confiuration. Table B register "fast_ppt_limit_mW_B" = "15000" @@ -48,10 +48,10 @@ chip soc/amd/mendocino register "slow_ppt_time_constant_s_B" = "5" register "stt_min_limit_B" = "10500" - register "stt_m1_B" = "0x18F" - register "stt_m2_B" = "0x48F" - register "stt_c_apu_B" = "0xECC5" - register "stt_skin_temp_apu_B" = "0x3300" + register "stt_m1_B" = "0xAE" + register "stt_m2_B" = "0xB8F" + register "stt_c_apu_B" = "0xC13B" + register "stt_skin_temp_apu_B" = "0x3000" # Set Dynamic DPTC thermal profile confiuration. Table C register "fast_ppt_limit_mW_C" = "30000" @@ -59,10 +59,10 @@ chip soc/amd/mendocino register "slow_ppt_time_constant_s_C" = "5" register "stt_min_limit_C" = "15000" - register "stt_m1_C" = "0x152" - register "stt_m2_C" = "0x4AE" - register "stt_c_apu_C" = "0xEE94" - register "stt_skin_temp_apu_C" = "0x3200" + register "stt_m1_C" = "0x129" + register "stt_m2_C" = "0xAF6" + register "stt_c_apu_C" = "0xC3D2" + register "stt_skin_temp_apu_C" = "0x3000" # Set Dynamic DPTC thermal profile confiuration. Table D register "fast_ppt_limit_mW_D" = "15000" @@ -70,10 +70,10 @@ chip soc/amd/mendocino register "slow_ppt_time_constant_s_D" = "5" register "stt_min_limit_D" = "10500" - register "stt_m1_D" = "0x152" - register "stt_m2_D" = "0x4AE" - register "stt_c_apu_D" = "0xEE94" - register "stt_skin_temp_apu_D" = "0x3300" + register "stt_m1_D" = "0x129" + register "stt_m2_D" = "0xAF6" + register "stt_c_apu_D" = "0xC3D2" + register "stt_skin_temp_apu_D" = "0x3000" # Set Dynamic DPTC thermal profile confiuration. Table E register "fast_ppt_limit_mW_E" = "24000" @@ -81,9 +81,9 @@ chip soc/amd/mendocino register "slow_ppt_time_constant_s_E" = "5" register "stt_min_limit_E" = "12000" - register "stt_m1_E" = "0x18F" - register "stt_m2_E" = "0x48F" - register "stt_c_apu_E" = "0xECC5" + register "stt_m1_E" = "0xAE" + register "stt_m2_E" = "0xB8F" + register "stt_c_apu_E" = "0xC13B" register "stt_skin_temp_apu_E" = "0x2F00" @@ -93,10 +93,10 @@ chip soc/amd/mendocino register "slow_ppt_time_constant_s_F" = "5" register "stt_min_limit_F" = "8000" - register "stt_m1_F" = "0x18F" - register "stt_m2_F" = "0x48F" - register "stt_c_apu_F" = "0xECC5" - register "stt_skin_temp_apu_F" = "0x3000" + register "stt_m1_F" = "0xAE" + register "stt_m2_F" = "0xB8F" + register "stt_c_apu_F" = "0xC13B" + register "stt_skin_temp_apu_F" = "0x2F00" register "i2c[0]" = "{ .speed = I2C_SPEED_FAST,