soc/intel/apollolake: Clean up code by using common CAR init
This patch currently contains common CAR initialization required in bootblock phase along with common MSR header - 1. Use SOC_INTEL_COMMON_BLOCK_CAR to have common CAR initialization and CAR teardown. 2. Use common MSR header "intelblocks/msr.h" inside soc/cpu.h Change-Id: I67f909f50a24f009b3e35388665251be1dde40f7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18555 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Subrata Banik
Martin Roth
parent
03e971cd23
commit
fc4c7d8320
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@ -50,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_LPSS_I2C
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select SOC_INTEL_COMMON_SMI
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select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
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@ -253,6 +254,7 @@ config NHLT_DA7219
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default n
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help
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Include DSP firmware settings for headset codec.
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choice
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prompt "Cache-as-ram implementation"
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default CAR_CQOS
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@ -261,6 +263,8 @@ choice
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config CAR_NEM
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bool "Non-evict mode"
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select SOC_INTEL_COMMON_BLOCK_CAR
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select INTEL_CAR_NEM
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help
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Traditionally, CAR is set up by using Non-Evict mode. This method
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does not allow CAR and cache to co-exist, because cache fills are
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@ -268,11 +272,19 @@ config CAR_NEM
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config CAR_CQOS
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bool "Cache Quality of Service"
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select SOC_INTEL_COMMON_BLOCK_CAR
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select INTEL_CAR_CQOS
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help
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Cache Quality of Service allows more fine-grained control of cache
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usage. As result, it is possible to set up portion of L2 cache for
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CAR and use remainder for actual caching.
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config USE_APOLLOLAKE_FSP_CAR
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bool "Use FSP CAR"
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select FSP_CAR
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help
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Use FSP APIs to initialize & tear Down the Cache-As-Ram.
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endchoice
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#
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@ -21,12 +21,7 @@ bootblock-y += pmutil.c
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bootblock-y += spi.c
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bootblock-y += tsc_freq.c
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bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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ifeq ($(CONFIG_FSP_CAR),y)
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bootblock-y += bootblock/cache_as_ram_fsp.S
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else
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bootblock-y += bootblock/cache_as_ram.S
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endif
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bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
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romstage-y += car.c
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
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@ -94,11 +89,7 @@ postcar-y += spi.c
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postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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postcar-y += tsc_freq.c
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ifeq ($(CONFIG_FSP_CAR),y)
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postcar-y += exit_car_fsp.S
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else
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postcar-y += exit_car.S
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endif
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postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
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verstage-y += car.c
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verstage-y += flash_ctrlr.c
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@ -1,251 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Intel Corp.
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci_def.h>
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#include <commonlib/helpers.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/cr.h>
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#include <cpu/x86/post_code.h>
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#include <soc/cpu.h>
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.global bootblock_pre_c_entry
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bootblock_pre_c_entry:
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.global cache_as_ram
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cache_as_ram:
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post_code(0x21)
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/* Clear/disable fixed MTRRs */
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mov $fixed_mtrr_list_size, %ebx
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xor %eax, %eax
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xor %edx, %edx
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clear_fixed_mtrr:
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add $-2, %ebx
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movzwl fixed_mtrr_list(%ebx), %ecx
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wrmsr
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jnz clear_fixed_mtrr
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post_code(0x22)
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/* Figure put how many MTRRs we have, and clear them out */
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mov $MTRR_CAP_MSR, %ecx
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rdmsr
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movzb %al, %ebx /* Number of variable MTRRs */
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mov $MTRR_PHYS_BASE(0), %ecx
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xor %eax, %eax
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xor %edx, %edx
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clear_var_mtrr:
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wrmsr
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inc %ecx
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wrmsr
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inc %ecx
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dec %ebx
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jnz clear_var_mtrr
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post_code(0x23)
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/* Configure default memory type to uncacheable (UC) */
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mov $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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/* Clear enable bits and set default type to UC. */
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and $~(MTRR_DEF_TYPE_MASK | MTRR_DEF_TYPE_EN | \
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MTRR_DEF_TYPE_FIX_EN), %eax
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wrmsr
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post_code(0x24)
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#if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0)
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/* Configure CAR region as write-back (WB) */
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mov $MTRR_PHYS_BASE(0), %ecx
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mov $CONFIG_DCACHE_RAM_BASE, %eax
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or $MTRR_TYPE_WRBACK, %eax
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xor %edx,%edx
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wrmsr
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/* Configure the MTRR mask for the size region */
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mov $MTRR_PHYS_MASK(0), %ecx
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mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */
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or $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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#elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */
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mov $MTRR_PHYS_BASE(0), %ecx
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mov $CONFIG_DCACHE_RAM_BASE, %eax
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or $MTRR_TYPE_WRBACK, %eax
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xor %edx,%edx
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wrmsr
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mov $MTRR_PHYS_MASK(0), %ecx
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mov $~(512 * KiB - 1), %eax /* size mask */
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or $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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mov $MTRR_PHYS_BASE(1), %ecx
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mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax
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or $MTRR_TYPE_WRBACK, %eax
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xor %edx,%edx
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wrmsr
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mov $MTRR_PHYS_MASK(1), %ecx
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mov $~(256 * KiB - 1), %eax /* size mask */
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or $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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#else
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#error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing"
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#endif
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post_code(0x25)
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/* Enable variable MTRRs */
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mov $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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or $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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/* Enable caching */
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mov %cr0, %eax
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and $~(CR0_CD | CR0_NW), %eax
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invd
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mov %eax, %cr0
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#if IS_ENABLED(CONFIG_CAR_NEM)
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/* Disable cache eviction (setup stage) */
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mov $MSR_EVICT_CTL, %ecx
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rdmsr
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or $0x1, %eax
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wrmsr
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#else
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/*
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* Disable both L1 and L2 prefetcher. For yet-to-understood reason,
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* prefetchers slow down filling cache with rep stos in CQOS mode.
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*/
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mov $MSR_PREFETCH_CTL, %ecx
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rdmsr
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or $(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax
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wrmsr
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#endif
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#if IS_ENABLED(CONFIG_CAR_CQOS)
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#if (CONFIG_DCACHE_RAM_SIZE == CONFIG_L2_CACHE_SIZE)
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/*
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* If CAR size is set to full L2 size, mask is calculated as all-zeros.
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* This is not supported by the CPU/uCode.
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*/
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#error "CQOS CAR may not use whole L2 cache area"
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#endif
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/* Calculate how many bits to be used for CAR */
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xor %edx, %edx
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mov $CONFIG_DCACHE_RAM_SIZE, %eax /* dividend */
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mov $CONFIG_CACHE_QOS_SIZE_PER_BIT, %ecx /* divisor */
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div %ecx /* result is in eax */
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mov %eax, %ecx /* save to ecx */
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mov $1, %ebx
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shl %cl, %ebx
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sub $1, %ebx /* resulting mask is is in ebx */
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/* Set this mask for initial cache fill */
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mov $MSR_L2_QOS_MASK(0), %ecx
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rdmsr
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mov %bl, %al
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wrmsr
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/* Set CLOS selector to 0 */
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mov $MSR_IA32_PQR_ASSOC, %ecx
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rdmsr
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and $~IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */
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wrmsr
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/* We will need to block CAR region from evicts */
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mov $MSR_L2_QOS_MASK(1), %ecx
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rdmsr
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/* Invert bits that are to be used for cache */
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mov %bl, %al
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xor $~0, %al /* invert 8 bits */
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wrmsr
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#endif
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post_code(0x26)
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/* Clear the cache memory region. This will also fill up the cache */
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mov $CONFIG_DCACHE_RAM_BASE, %edi
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mov $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx
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xor %eax, %eax
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rep stos %eax, %es:(%edi)
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post_code(0x27)
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#if IS_ENABLED(CONFIG_CAR_NEM)
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/* Disable cache eviction (run stage) */
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mov $MSR_EVICT_CTL, %ecx
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rdmsr
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or $0x2, %eax
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wrmsr
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#else
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/* Cache is populated. Use mask 1 that will block evicts */
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mov $MSR_IA32_PQR_ASSOC, %ecx
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rdmsr
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and $~IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */
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or $1, %edx /* select mask 1 */
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wrmsr
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/* Enable prefetchers */
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mov $MSR_PREFETCH_CTL, %ecx
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rdmsr
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and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax
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wrmsr
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#endif
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post_code(0x28)
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car_init_done:
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/* Setup bootblock stack */
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mov $_car_stack_end, %esp
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before_carstage:
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post_code(0x2b)
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/* Restore the timestamp from bootblock_crt0.S (mm2:mm1) */
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movd %mm2, %eax
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push %eax
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movd %mm1, %eax
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push %eax
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/* We can call into C functions now */
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call bootblock_c_entry
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/* Never reached */
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.halt_forever:
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post_code(POST_DEAD_CODE)
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hlt
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jmp .halt_forever
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fixed_mtrr_list:
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.word MTRR_FIX_64K_00000
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.word MTRR_FIX_16K_80000
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.word MTRR_FIX_16K_A0000
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.word MTRR_FIX_4K_C0000
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.word MTRR_FIX_4K_C8000
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.word MTRR_FIX_4K_D0000
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.word MTRR_FIX_4K_D8000
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.word MTRR_FIX_4K_E0000
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.word MTRR_FIX_4K_E8000
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.word MTRR_FIX_4K_F0000
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.word MTRR_FIX_4K_F8000
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fixed_mtrr_list_size = . - fixed_mtrr_list
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@ -1,68 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cr.h>
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#include <soc/cpu.h>
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.text
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.global chipset_teardown_car
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chipset_teardown_car:
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/*
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* Retrieve return address from stack as it will get trashed below if
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* execution is utilizing the cache-as-ram stack.
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*/
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pop %ebx
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/* Disable MTRRs. */
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mov $(MTRR_DEF_TYPE_MSR), %ecx
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rdmsr
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and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax
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wrmsr
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#if IS_ENABLED(CONFIG_CAR_CQOS)
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/* Go back to all-evicting mode, set both masks to all-1s */
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mov $MSR_L2_QOS_MASK(0), %ecx
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rdmsr
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mov $~0, %al
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wrmsr
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mov $MSR_L2_QOS_MASK(1), %ecx
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rdmsr
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mov $~0, %al
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wrmsr
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/* Reset CLOS selector to 0 */
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mov $MSR_IA32_PQR_ASSOC, %ecx
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rdmsr
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and $~IA32_PQR_ASSOC_MASK, %edx
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wrmsr
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#endif
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/* invalidate cache contents. */
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invd
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#if IS_ENABLED(CONFIG_CAR_NEM)
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/* Knock down bit 1 then bit 0 of NEM control not combining steps. */
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mov $(MSR_EVICT_CTL), %ecx
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rdmsr
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and $(~(1 << 1)), %eax
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wrmsr
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and $(~(1 << 0)), %eax
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wrmsr
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#endif
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/* Return to caller. */
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jmp *%ebx
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@ -18,6 +18,8 @@
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#ifndef _SOC_APOLLOLAKE_CPU_H_
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#define _SOC_APOLLOLAKE_CPU_H_
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#include <intelblocks/msr.h>
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#ifndef __ASSEMBLER__
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#include <cpu/x86/msr.h>
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#include <device/device.h>
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@ -30,64 +32,10 @@ void enable_untrusted_mode(void);
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#define CPUID_APOLLOLAKE_A0 0x506c8
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#define CPUID_APOLLOLAKE_B0 0x506c9
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#define MSR_PLATFORM_INFO 0xce
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#define MSR_POWER_MISC 0x120
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#define ENABLE_IA_UNTRUSTED (1 << 6)
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#define FLUSH_DL1_L2 (1 << 8)
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#define MSR_CORE_THREAD_COUNT 0x35
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#define MSR_EVICT_CTL 0x2e0
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#define MSR_EMULATE_PM_TMR 0x121
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#define EMULATE_PM_TMR_EN (1 << 16)
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#define MSR_PREFETCH_CTL 0x1a4
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#define PREFETCH_L1_DISABLE (1 << 0)
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#define PREFETCH_L2_DISABLE (1 << 2)
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#define MSR_PKG_POWER_SKU_UNIT 0x606
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#define MSR_PKG_POWER_SKU 0x614
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#define MSR_PKG_POWER_LIMIT 0x610
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#define PKG_POWER_LIMIT_MASK (0x7fff)
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#define PKG_POWER_LIMIT_EN (1 << 15)
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#define PKG_POWER_LIMIT_CLAMP (1 << 16)
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#define PKG_POWER_LIMIT_TIME_SHIFT 17
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#define PKG_POWER_LIMIT_TIME_MASK (0x7f)
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/*
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* For Mobile, RAPL default PL1 time window value set to 28 seconds.
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* RAPL time window calculation defined as follows:
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* Time Window = (float)((1+X/4)*(2*^Y), X Corresponds to [23:22],
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* Y to [21:17] in MSR 0x610. 28 sec is equal to 0x6e.
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*/
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#define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e
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/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */
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#define PKG_C_STATE_LIMIT_C2_MASK 0x2
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/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/
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#define CORE_C_STATE_LIMIT_C10_MASK 0x70
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/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */
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#define IO_MWAIT_REDIRECT_MASK 0x400
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/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */
|
||||
#define CST_CFG_LOCK_MASK 0x8000
|
||||
|
||||
#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
|
||||
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
|
||||
#define MSR_FEATURE_CONFIG 0x13c
|
||||
#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL
|
||||
#define FEATURE_CONFIG_LOCK (1 << 0)
|
||||
#define MSR_POWER_CTL 0x1fc
|
||||
|
||||
#define MSR_L2_QOS_MASK(reg) (0xd10 + reg)
|
||||
#define MSR_IA32_PQR_ASSOC 0xc8f
|
||||
/* MSR bits 33:32 encode slot number 0-3 */
|
||||
#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1)
|
||||
/* 16 way cache, 8 bits per QOS, 64 byte cache line, 1024 sets */
|
||||
#define CACHE_WAYS 16
|
||||
#define CACHE_BITS_PER_MASK 8
|
||||
#define CACHE_LINE_SIZE 64
|
||||
#define CACHE_SETS 1024
|
||||
|
||||
#define BASE_CLOCK_MHZ 100
|
||||
|
||||
/* Common Timer Copy (CTC) frequency - 19.2MHz. */
|
||||
#define CTC_FREQ 19200000
|
||||
#define CTC_FREQ 19200000
|
||||
|
||||
/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */
|
||||
#define APL_BURST_MODE_DISABLE 0x40
|
||||
|
|
|
|||
Loading…
Reference in New Issue