soc/intel/apollolake: Clean up code by using common CAR init
This patch currently contains common CAR initialization required in bootblock phase along with common MSR header - 1. Use SOC_INTEL_COMMON_BLOCK_CAR to have common CAR initialization and CAR teardown. 2. Use common MSR header "intelblocks/msr.h" inside soc/cpu.h Change-Id: I67f909f50a24f009b3e35388665251be1dde40f7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18555 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Subrata Banik
Martin Roth
parent
03e971cd23
commit
fc4c7d8320
|
|
@ -50,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS
|
|||
select SOC_INTEL_COMMON
|
||||
select SOC_INTEL_COMMON_ACPI
|
||||
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
|
||||
select SOC_INTEL_COMMON_BLOCK
|
||||
select SOC_INTEL_COMMON_LPSS_I2C
|
||||
select SOC_INTEL_COMMON_SMI
|
||||
select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
|
||||
|
|
@ -253,6 +254,7 @@ config NHLT_DA7219
|
|||
default n
|
||||
help
|
||||
Include DSP firmware settings for headset codec.
|
||||
|
||||
choice
|
||||
prompt "Cache-as-ram implementation"
|
||||
default CAR_CQOS
|
||||
|
|
@ -261,6 +263,8 @@ choice
|
|||
|
||||
config CAR_NEM
|
||||
bool "Non-evict mode"
|
||||
select SOC_INTEL_COMMON_BLOCK_CAR
|
||||
select INTEL_CAR_NEM
|
||||
help
|
||||
Traditionally, CAR is set up by using Non-Evict mode. This method
|
||||
does not allow CAR and cache to co-exist, because cache fills are
|
||||
|
|
@ -268,11 +272,19 @@ config CAR_NEM
|
|||
|
||||
config CAR_CQOS
|
||||
bool "Cache Quality of Service"
|
||||
select SOC_INTEL_COMMON_BLOCK_CAR
|
||||
select INTEL_CAR_CQOS
|
||||
help
|
||||
Cache Quality of Service allows more fine-grained control of cache
|
||||
usage. As result, it is possible to set up portion of L2 cache for
|
||||
CAR and use remainder for actual caching.
|
||||
|
||||
config USE_APOLLOLAKE_FSP_CAR
|
||||
bool "Use FSP CAR"
|
||||
select FSP_CAR
|
||||
help
|
||||
Use FSP APIs to initialize & tear Down the Cache-As-Ram.
|
||||
|
||||
endchoice
|
||||
|
||||
#
|
||||
|
|
|
|||
|
|
@ -21,12 +21,7 @@ bootblock-y += pmutil.c
|
|||
bootblock-y += spi.c
|
||||
bootblock-y += tsc_freq.c
|
||||
bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
|
||||
|
||||
ifeq ($(CONFIG_FSP_CAR),y)
|
||||
bootblock-y += bootblock/cache_as_ram_fsp.S
|
||||
else
|
||||
bootblock-y += bootblock/cache_as_ram.S
|
||||
endif
|
||||
bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
|
||||
|
||||
romstage-y += car.c
|
||||
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
|
||||
|
|
@ -94,11 +89,7 @@ postcar-y += spi.c
|
|||
postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
|
||||
postcar-y += tsc_freq.c
|
||||
|
||||
ifeq ($(CONFIG_FSP_CAR),y)
|
||||
postcar-y += exit_car_fsp.S
|
||||
else
|
||||
postcar-y += exit_car.S
|
||||
endif
|
||||
postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
|
||||
|
||||
verstage-y += car.c
|
||||
verstage-y += flash_ctrlr.c
|
||||
|
|
|
|||
|
|
@ -1,251 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015-2016 Intel Corp.
|
||||
* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
|
||||
* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci_def.h>
|
||||
#include <commonlib/helpers.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/cr.h>
|
||||
#include <cpu/x86/post_code.h>
|
||||
#include <soc/cpu.h>
|
||||
|
||||
.global bootblock_pre_c_entry
|
||||
bootblock_pre_c_entry:
|
||||
|
||||
.global cache_as_ram
|
||||
cache_as_ram:
|
||||
post_code(0x21)
|
||||
|
||||
/* Clear/disable fixed MTRRs */
|
||||
mov $fixed_mtrr_list_size, %ebx
|
||||
xor %eax, %eax
|
||||
xor %edx, %edx
|
||||
clear_fixed_mtrr:
|
||||
add $-2, %ebx
|
||||
movzwl fixed_mtrr_list(%ebx), %ecx
|
||||
wrmsr
|
||||
jnz clear_fixed_mtrr
|
||||
|
||||
post_code(0x22)
|
||||
|
||||
/* Figure put how many MTRRs we have, and clear them out */
|
||||
mov $MTRR_CAP_MSR, %ecx
|
||||
rdmsr
|
||||
movzb %al, %ebx /* Number of variable MTRRs */
|
||||
mov $MTRR_PHYS_BASE(0), %ecx
|
||||
xor %eax, %eax
|
||||
xor %edx, %edx
|
||||
|
||||
clear_var_mtrr:
|
||||
wrmsr
|
||||
inc %ecx
|
||||
wrmsr
|
||||
inc %ecx
|
||||
dec %ebx
|
||||
jnz clear_var_mtrr
|
||||
|
||||
post_code(0x23)
|
||||
|
||||
/* Configure default memory type to uncacheable (UC) */
|
||||
mov $MTRR_DEF_TYPE_MSR, %ecx
|
||||
rdmsr
|
||||
/* Clear enable bits and set default type to UC. */
|
||||
and $~(MTRR_DEF_TYPE_MASK | MTRR_DEF_TYPE_EN | \
|
||||
MTRR_DEF_TYPE_FIX_EN), %eax
|
||||
wrmsr
|
||||
|
||||
post_code(0x24)
|
||||
|
||||
#if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0)
|
||||
/* Configure CAR region as write-back (WB) */
|
||||
mov $MTRR_PHYS_BASE(0), %ecx
|
||||
mov $CONFIG_DCACHE_RAM_BASE, %eax
|
||||
or $MTRR_TYPE_WRBACK, %eax
|
||||
xor %edx,%edx
|
||||
wrmsr
|
||||
|
||||
/* Configure the MTRR mask for the size region */
|
||||
mov $MTRR_PHYS_MASK(0), %ecx
|
||||
mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */
|
||||
or $MTRR_PHYS_MASK_VALID, %eax
|
||||
wrmsr
|
||||
#elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */
|
||||
mov $MTRR_PHYS_BASE(0), %ecx
|
||||
mov $CONFIG_DCACHE_RAM_BASE, %eax
|
||||
or $MTRR_TYPE_WRBACK, %eax
|
||||
xor %edx,%edx
|
||||
wrmsr
|
||||
|
||||
mov $MTRR_PHYS_MASK(0), %ecx
|
||||
mov $~(512 * KiB - 1), %eax /* size mask */
|
||||
or $MTRR_PHYS_MASK_VALID, %eax
|
||||
wrmsr
|
||||
|
||||
mov $MTRR_PHYS_BASE(1), %ecx
|
||||
mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax
|
||||
or $MTRR_TYPE_WRBACK, %eax
|
||||
xor %edx,%edx
|
||||
wrmsr
|
||||
|
||||
mov $MTRR_PHYS_MASK(1), %ecx
|
||||
mov $~(256 * KiB - 1), %eax /* size mask */
|
||||
or $MTRR_PHYS_MASK_VALID, %eax
|
||||
wrmsr
|
||||
#else
|
||||
#error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing"
|
||||
#endif
|
||||
|
||||
post_code(0x25)
|
||||
|
||||
/* Enable variable MTRRs */
|
||||
mov $MTRR_DEF_TYPE_MSR, %ecx
|
||||
rdmsr
|
||||
or $MTRR_DEF_TYPE_EN, %eax
|
||||
wrmsr
|
||||
|
||||
/* Enable caching */
|
||||
mov %cr0, %eax
|
||||
and $~(CR0_CD | CR0_NW), %eax
|
||||
invd
|
||||
mov %eax, %cr0
|
||||
|
||||
#if IS_ENABLED(CONFIG_CAR_NEM)
|
||||
/* Disable cache eviction (setup stage) */
|
||||
mov $MSR_EVICT_CTL, %ecx
|
||||
rdmsr
|
||||
or $0x1, %eax
|
||||
wrmsr
|
||||
#else
|
||||
/*
|
||||
* Disable both L1 and L2 prefetcher. For yet-to-understood reason,
|
||||
* prefetchers slow down filling cache with rep stos in CQOS mode.
|
||||
*/
|
||||
mov $MSR_PREFETCH_CTL, %ecx
|
||||
rdmsr
|
||||
or $(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax
|
||||
wrmsr
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_CAR_CQOS)
|
||||
#if (CONFIG_DCACHE_RAM_SIZE == CONFIG_L2_CACHE_SIZE)
|
||||
/*
|
||||
* If CAR size is set to full L2 size, mask is calculated as all-zeros.
|
||||
* This is not supported by the CPU/uCode.
|
||||
*/
|
||||
#error "CQOS CAR may not use whole L2 cache area"
|
||||
#endif
|
||||
/* Calculate how many bits to be used for CAR */
|
||||
xor %edx, %edx
|
||||
mov $CONFIG_DCACHE_RAM_SIZE, %eax /* dividend */
|
||||
mov $CONFIG_CACHE_QOS_SIZE_PER_BIT, %ecx /* divisor */
|
||||
div %ecx /* result is in eax */
|
||||
mov %eax, %ecx /* save to ecx */
|
||||
mov $1, %ebx
|
||||
shl %cl, %ebx
|
||||
sub $1, %ebx /* resulting mask is is in ebx */
|
||||
|
||||
/* Set this mask for initial cache fill */
|
||||
mov $MSR_L2_QOS_MASK(0), %ecx
|
||||
rdmsr
|
||||
mov %bl, %al
|
||||
wrmsr
|
||||
|
||||
/* Set CLOS selector to 0 */
|
||||
mov $MSR_IA32_PQR_ASSOC, %ecx
|
||||
rdmsr
|
||||
and $~IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */
|
||||
wrmsr
|
||||
|
||||
/* We will need to block CAR region from evicts */
|
||||
mov $MSR_L2_QOS_MASK(1), %ecx
|
||||
rdmsr
|
||||
/* Invert bits that are to be used for cache */
|
||||
mov %bl, %al
|
||||
xor $~0, %al /* invert 8 bits */
|
||||
wrmsr
|
||||
#endif
|
||||
post_code(0x26)
|
||||
|
||||
/* Clear the cache memory region. This will also fill up the cache */
|
||||
mov $CONFIG_DCACHE_RAM_BASE, %edi
|
||||
mov $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx
|
||||
xor %eax, %eax
|
||||
rep stos %eax, %es:(%edi)
|
||||
|
||||
post_code(0x27)
|
||||
|
||||
#if IS_ENABLED(CONFIG_CAR_NEM)
|
||||
/* Disable cache eviction (run stage) */
|
||||
mov $MSR_EVICT_CTL, %ecx
|
||||
rdmsr
|
||||
or $0x2, %eax
|
||||
wrmsr
|
||||
#else
|
||||
/* Cache is populated. Use mask 1 that will block evicts */
|
||||
mov $MSR_IA32_PQR_ASSOC, %ecx
|
||||
rdmsr
|
||||
and $~IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */
|
||||
or $1, %edx /* select mask 1 */
|
||||
wrmsr
|
||||
|
||||
/* Enable prefetchers */
|
||||
mov $MSR_PREFETCH_CTL, %ecx
|
||||
rdmsr
|
||||
and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax
|
||||
wrmsr
|
||||
#endif
|
||||
|
||||
post_code(0x28)
|
||||
|
||||
car_init_done:
|
||||
|
||||
/* Setup bootblock stack */
|
||||
mov $_car_stack_end, %esp
|
||||
|
||||
before_carstage:
|
||||
post_code(0x2b)
|
||||
|
||||
/* Restore the timestamp from bootblock_crt0.S (mm2:mm1) */
|
||||
movd %mm2, %eax
|
||||
push %eax
|
||||
movd %mm1, %eax
|
||||
push %eax
|
||||
|
||||
/* We can call into C functions now */
|
||||
call bootblock_c_entry
|
||||
|
||||
/* Never reached */
|
||||
|
||||
.halt_forever:
|
||||
post_code(POST_DEAD_CODE)
|
||||
hlt
|
||||
jmp .halt_forever
|
||||
|
||||
fixed_mtrr_list:
|
||||
.word MTRR_FIX_64K_00000
|
||||
.word MTRR_FIX_16K_80000
|
||||
.word MTRR_FIX_16K_A0000
|
||||
.word MTRR_FIX_4K_C0000
|
||||
.word MTRR_FIX_4K_C8000
|
||||
.word MTRR_FIX_4K_D0000
|
||||
.word MTRR_FIX_4K_D8000
|
||||
.word MTRR_FIX_4K_E0000
|
||||
.word MTRR_FIX_4K_E8000
|
||||
.word MTRR_FIX_4K_F0000
|
||||
.word MTRR_FIX_4K_F8000
|
||||
fixed_mtrr_list_size = . - fixed_mtrr_list
|
||||
|
|
@ -1,68 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/cr.h>
|
||||
#include <soc/cpu.h>
|
||||
|
||||
.text
|
||||
.global chipset_teardown_car
|
||||
chipset_teardown_car:
|
||||
/*
|
||||
* Retrieve return address from stack as it will get trashed below if
|
||||
* execution is utilizing the cache-as-ram stack.
|
||||
*/
|
||||
pop %ebx
|
||||
|
||||
/* Disable MTRRs. */
|
||||
mov $(MTRR_DEF_TYPE_MSR), %ecx
|
||||
rdmsr
|
||||
and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax
|
||||
wrmsr
|
||||
|
||||
#if IS_ENABLED(CONFIG_CAR_CQOS)
|
||||
/* Go back to all-evicting mode, set both masks to all-1s */
|
||||
mov $MSR_L2_QOS_MASK(0), %ecx
|
||||
rdmsr
|
||||
mov $~0, %al
|
||||
wrmsr
|
||||
|
||||
mov $MSR_L2_QOS_MASK(1), %ecx
|
||||
rdmsr
|
||||
mov $~0, %al
|
||||
wrmsr
|
||||
|
||||
/* Reset CLOS selector to 0 */
|
||||
mov $MSR_IA32_PQR_ASSOC, %ecx
|
||||
rdmsr
|
||||
and $~IA32_PQR_ASSOC_MASK, %edx
|
||||
wrmsr
|
||||
#endif
|
||||
/* invalidate cache contents. */
|
||||
invd
|
||||
|
||||
#if IS_ENABLED(CONFIG_CAR_NEM)
|
||||
/* Knock down bit 1 then bit 0 of NEM control not combining steps. */
|
||||
mov $(MSR_EVICT_CTL), %ecx
|
||||
rdmsr
|
||||
and $(~(1 << 1)), %eax
|
||||
wrmsr
|
||||
and $(~(1 << 0)), %eax
|
||||
wrmsr
|
||||
#endif
|
||||
|
||||
/* Return to caller. */
|
||||
jmp *%ebx
|
||||
|
|
@ -18,6 +18,8 @@
|
|||
#ifndef _SOC_APOLLOLAKE_CPU_H_
|
||||
#define _SOC_APOLLOLAKE_CPU_H_
|
||||
|
||||
#include <intelblocks/msr.h>
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <device/device.h>
|
||||
|
|
@ -30,60 +32,6 @@ void enable_untrusted_mode(void);
|
|||
#define CPUID_APOLLOLAKE_A0 0x506c8
|
||||
#define CPUID_APOLLOLAKE_B0 0x506c9
|
||||
|
||||
#define MSR_PLATFORM_INFO 0xce
|
||||
#define MSR_POWER_MISC 0x120
|
||||
#define ENABLE_IA_UNTRUSTED (1 << 6)
|
||||
#define FLUSH_DL1_L2 (1 << 8)
|
||||
#define MSR_CORE_THREAD_COUNT 0x35
|
||||
#define MSR_EVICT_CTL 0x2e0
|
||||
#define MSR_EMULATE_PM_TMR 0x121
|
||||
#define EMULATE_PM_TMR_EN (1 << 16)
|
||||
#define MSR_PREFETCH_CTL 0x1a4
|
||||
#define PREFETCH_L1_DISABLE (1 << 0)
|
||||
#define PREFETCH_L2_DISABLE (1 << 2)
|
||||
|
||||
#define MSR_PKG_POWER_SKU_UNIT 0x606
|
||||
#define MSR_PKG_POWER_SKU 0x614
|
||||
#define MSR_PKG_POWER_LIMIT 0x610
|
||||
#define PKG_POWER_LIMIT_MASK (0x7fff)
|
||||
#define PKG_POWER_LIMIT_EN (1 << 15)
|
||||
#define PKG_POWER_LIMIT_CLAMP (1 << 16)
|
||||
#define PKG_POWER_LIMIT_TIME_SHIFT 17
|
||||
#define PKG_POWER_LIMIT_TIME_MASK (0x7f)
|
||||
/*
|
||||
* For Mobile, RAPL default PL1 time window value set to 28 seconds.
|
||||
* RAPL time window calculation defined as follows:
|
||||
* Time Window = (float)((1+X/4)*(2*^Y), X Corresponds to [23:22],
|
||||
* Y to [21:17] in MSR 0x610. 28 sec is equal to 0x6e.
|
||||
*/
|
||||
#define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e
|
||||
|
||||
/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */
|
||||
#define PKG_C_STATE_LIMIT_C2_MASK 0x2
|
||||
/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/
|
||||
#define CORE_C_STATE_LIMIT_C10_MASK 0x70
|
||||
/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */
|
||||
#define IO_MWAIT_REDIRECT_MASK 0x400
|
||||
/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */
|
||||
#define CST_CFG_LOCK_MASK 0x8000
|
||||
|
||||
#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
|
||||
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
|
||||
#define MSR_FEATURE_CONFIG 0x13c
|
||||
#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL
|
||||
#define FEATURE_CONFIG_LOCK (1 << 0)
|
||||
#define MSR_POWER_CTL 0x1fc
|
||||
|
||||
#define MSR_L2_QOS_MASK(reg) (0xd10 + reg)
|
||||
#define MSR_IA32_PQR_ASSOC 0xc8f
|
||||
/* MSR bits 33:32 encode slot number 0-3 */
|
||||
#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1)
|
||||
/* 16 way cache, 8 bits per QOS, 64 byte cache line, 1024 sets */
|
||||
#define CACHE_WAYS 16
|
||||
#define CACHE_BITS_PER_MASK 8
|
||||
#define CACHE_LINE_SIZE 64
|
||||
#define CACHE_SETS 1024
|
||||
|
||||
#define BASE_CLOCK_MHZ 100
|
||||
|
||||
/* Common Timer Copy (CTC) frequency - 19.2MHz. */
|
||||
|
|
|
|||
Loading…
Reference in New Issue