mb/google/hatch: Add USB port capability ACPI support for USB2 port10
This implementation adds support to create ACPI package for USB port capability (_UPC) and physical location of device (_PLD) for USB2 port 10. BUG🅱️123375275 TEST:Verify _UPC and _PLD ACPI packages gets published for USB2 Port 10 in SSDT and BT is functional in discrete and integrated mode. Change-Id: Ifeab24505a700e8e4677be20074c7d0400769cec Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/31197 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -5,6 +5,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_SPI_ACPI
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select DRIVERS_USB_ACPI
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_LPC
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select HAVE_ACPI_RESUME
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@ -134,7 +134,7 @@ chip soc/intel/cannonlake
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device usb 2.3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""Bluetooth""
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register "desc" = ""Discrete bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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device usb 2.4 on end
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end
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@ -148,6 +148,11 @@ chip soc/intel/cannonlake
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register "type" = "UPC_TYPE_INTERNAL"
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device usb 2.6 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""Integrated CnVi bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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device usb 2.9 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""Left Type-C Port""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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