mb/google/hatch: Add USB port capability ACPI support for USB2 port10

This implementation adds support to create ACPI package for USB port
capability (_UPC) and physical location of device (_PLD) for USB2 port 10.

BUG🅱️123375275
TEST:Verify _UPC and _PLD ACPI packages gets published for USB2 Port 10
     in SSDT and BT is functional in discrete and integrated mode.

Change-Id: Ifeab24505a700e8e4677be20074c7d0400769cec
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/31197
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra 2019-02-01 18:15:17 +05:30 committed by Subrata Banik
parent f56249ba0b
commit fc63b8bbc0
2 changed files with 7 additions and 1 deletions

View File

@ -5,6 +5,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_SPI_ACPI
select DRIVERS_USB_ACPI
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME

View File

@ -134,7 +134,7 @@ chip soc/intel/cannonlake
device usb 2.3 on end
end
chip drivers/usb/acpi
register "desc" = ""Bluetooth""
register "desc" = ""Discrete bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
device usb 2.4 on end
end
@ -148,6 +148,11 @@ chip soc/intel/cannonlake
register "type" = "UPC_TYPE_INTERNAL"
device usb 2.6 on end
end
chip drivers/usb/acpi
register "desc" = ""Integrated CnVi bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
device usb 2.9 on end
end
chip drivers/usb/acpi
register "desc" = ""Left Type-C Port""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"