mb/google/zork/vilboz: Enable SAR proximity sensor STH9324
BUG=b:161759253 BRANCH=firmware-zork-13434.B TEST=emerge-zork coreboot chromeos-bootimage firmware log: \_SB.I2C2.SEMTECH SX9324: SAR Proximity Sensor at I2C: 02:28 kernel log: INFO kernel: [ 11.238644] sx932x i2c-STH9324:00: initial compensation success Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I6294ce291365443dd1c4550ba75cb7f33481b889 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45565 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -16,6 +16,11 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
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PAD_GPO(GPIO_140, HIGH),
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PAD_GPO(GPIO_140, HIGH),
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};
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};
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static const struct soc_amd_gpio vilboz_gpio_set_stage_ram[] = {
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/* P sensor INT */
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PAD_INT(GPIO_40, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY),
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};
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const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
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const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
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{
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{
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uint32_t board_version;
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uint32_t board_version;
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@ -33,6 +38,6 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
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return bid_1_gpio_set_stage_ram;
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return bid_1_gpio_set_stage_ram;
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}
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}
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*size = 0;
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*size = ARRAY_SIZE(vilboz_gpio_set_stage_ram);
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return NULL;
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return vilboz_gpio_set_stage_ram;
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}
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}
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@ -142,5 +142,12 @@ chip soc/amd/picasso
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register "hid_desc_reg_offset" = "0x20"
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register "hid_desc_reg_offset" = "0x20"
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device i2c 2c on end
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device i2c 2c on end
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end
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end
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chip drivers/i2c/generic
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register "hid" = ""STH9324""
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register "name" = ""SEMTECH SX9324""
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register "desc" = ""SAR Proximity Sensor""
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register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)"
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device i2c 28 on end
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end
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end
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end
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end # chip soc/amd/picasso
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end # chip soc/amd/picasso
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