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soc/amd/stoneyridge: use common AMD CPU power state ACPI generation 

Instead of using the PSTATE SSDT generated by binaryPI, use the common
AMD code by selecting SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE. To
match the SSDT from binaryPI, set ACPI_SSDT_PSD_INDEPENDENT to n. There
are two differences to the binaryPI SSDT: Now coreboot includes the C1
state in the _CST package instead of just having the kernel add this due
to the ACPI_FADT_C1_SUPPORTED bit being set and the address of the
PS_STS_REG P state status MSR is written to the corresponding field of
the _PCT package instead of being 0.

TEST=On Careena the new P and C state ACPI packages are nearly identical
to the ones from the SSDT from binaryPI with the two functional
differences mentioned above.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icdf6bc8f0e0363f185a294ab84edcb51322e7eb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This commit is contained in:
Felix Held 2023-03-24 21:41:35 +01:00
parent 7d8c832d1f
commit fc709fee09
3 changed files with 4 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/amd/stoneyridge/Kconfig
View File

@ -21,6 +21,7 @@ config SOC_AMD_STONEYRIDGE
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACPI
select SOC_AMD_COMMON_BLOCK_ACPI_GPIO
select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM
select SOC_AMD_COMMON_BLOCK_AOAC
@ -269,6 +270,9 @@ config ACPI_CPU_STRING
string
default "\\_SB.P%03d"
config ACPI_SSDT_PSD_INDEPENDENT
default n
config ACPI_BERT
bool "Build ACPI BERT Table"
default y

16
src/soc/amd/stoneyridge/acpi.c
View File

@ -111,19 +111,3 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size)
*size = ARRAY_SIZE(cstate_cfg_table);
return cstate_cfg_table;
}
void generate_cpu_entries(const struct device *device)
{
int cpu;
const int cores = get_cpu_count();
printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores);
/* Generate \_SB.Pxxx */
for (cpu = 0; cpu < cores; cpu++) {
acpigen_write_processor_device(cpu);
acpigen_write_processor_device_end();
}
acpigen_write_processor_package("PPKG", 0, cores);
}

13
src/soc/amd/stoneyridge/northbridge.c
View File

@ -213,7 +213,6 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
{
acpi_srat_t *srat;
acpi_slit_t *slit;
acpi_header_t *ssdt;
acpi_header_t *alib;
acpi_header_t *ivrs;
acpi_hest_t *hest;
@ -277,18 +276,6 @@ static unsigned long agesa_write_acpi_tables(const struct device *device,
" Skipping.\n");
}
current = acpi_align_current(current);
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE);
if (ssdt != NULL) {
memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *)current;
current += ssdt->length;
} else {
printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n");
}
acpi_add_table(rsdp, ssdt);
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
return current;
}