diff --git a/src/mainboard/google/slippy/variants/falco/overridetree.cb b/src/mainboard/google/slippy/variants/falco/overridetree.cb
index fc77345dab..b9f99a3a4d 100644
--- a/src/mainboard/google/slippy/variants/falco/overridetree.cb
+++ b/src/mainboard/google/slippy/variants/falco/overridetree.cb
@@ -13,8 +13,10 @@ chip northbridge/intel/haswell
 
 		chip southbridge/intel/lynxpoint
 
-			# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
-			register "icc_clock_disable" = "0x013e0000"
+			device pci 16.0 on # Management Engine Interface 1
+				# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
+				register "icc_clock_disable" = "0x013e0000"
+			end
 		end
 	end
 end
diff --git a/src/mainboard/google/slippy/variants/peppy/overridetree.cb b/src/mainboard/google/slippy/variants/peppy/overridetree.cb
index e732a9270c..bb30f763f3 100644
--- a/src/mainboard/google/slippy/variants/peppy/overridetree.cb
+++ b/src/mainboard/google/slippy/variants/peppy/overridetree.cb
@@ -13,12 +13,16 @@ chip northbridge/intel/haswell
 
 		chip southbridge/intel/lynxpoint
 
-			# DTLE DATA / EDGE values
-			register "sata_port0_gen3_dtle" = "0x5"
-			register "sata_port1_gen3_dtle" = "0x5"
+			device pci 1f.2 on # SATA Controller
+				# DTLE DATA / EDGE values
+				register "sata_port0_gen3_dtle" = "0x5"
+				register "sata_port1_gen3_dtle" = "0x5"
+			end
 
-			# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
-			register "icc_clock_disable" = "0x013c0000"
+			device pci 16.0 on # Management Engine Interface 1
+				# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
+				register "icc_clock_disable" = "0x013c0000"
+			end
 		end
 	end
 end
diff --git a/src/mainboard/google/slippy/variants/wolf/overridetree.cb b/src/mainboard/google/slippy/variants/wolf/overridetree.cb
index 824694720d..b2a766684e 100644
--- a/src/mainboard/google/slippy/variants/wolf/overridetree.cb
+++ b/src/mainboard/google/slippy/variants/wolf/overridetree.cb
@@ -13,14 +13,18 @@ chip northbridge/intel/haswell
 
 		chip southbridge/intel/lynxpoint
 
-			register "sata_devslp_disable" = "0x1"
+			device pci 1f.2 on # SATA Controller
+				register "sata_devslp_disable" = "0x1"
 
-			# DTLE DATA / EDGE values
-			register "sata_port0_gen3_dtle" = "0x5"
-			register "sata_port1_gen3_dtle" = "0x5"
+				# DTLE DATA / EDGE values
+				register "sata_port0_gen3_dtle" = "0x5"
+				register "sata_port1_gen3_dtle" = "0x5"
+			end
 
-			# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
-			register "icc_clock_disable" = "0x013c0000"
+			device pci 16.0 on # Management Engine Interface 1
+				# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
+				register "icc_clock_disable" = "0x013c0000"
+			end
 		end
 	end
 end