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biostar/am1ml: Switch away from ROMCC_BOOTBLOCK 

Switching was done by moving a SIO configuration and
a clocks setup from 'romstage.c' to 'bootblock.c'

TEST=Boots into Ubuntu Linux 16.04.6 without a problem.

Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f
Signed-off-by: Sergej Ivanov <getinaks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Sergej Ivanov 2019-12-13 23:04:47 +00:00 committed by Kyösti Mälkki
parent 9c6e9c684f
commit fc749b23ef
5 changed files with 14 additions and 69 deletions
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3
src/mainboard/biostar/Kconfig
View File

@ -20,9 +20,6 @@ choice
source "src/mainboard/biostar/*/Kconfig.name" source "src/mainboard/biostar/*/Kconfig.name"
config BIOSTAR_BOARDS_DISABLED
bool "Boards from vendor are disabled"
endchoice endchoice
source "src/mainboard/biostar/*/Kconfig" source "src/mainboard/biostar/*/Kconfig"

4
src/mainboard/biostar/am1ml/Kconfig
View File

@ -14,15 +14,11 @@
# GNU General Public License for more details. # GNU General Public License for more details.
# #
config BOARD_BIOSTAR_AM1ML
def_bool n
if BOARD_BIOSTAR_AM1ML if BOARD_BIOSTAR_AM1ML
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select BOARD_ROMSIZE_KB_4096 select BOARD_ROMSIZE_KB_4096
#select ROMCC_BOOTBLOCK
select CPU_AMD_AGESA_FAMILY16_KB select CPU_AMD_AGESA_FAMILY16_KB
select FORCE_AM1_SOCKET_SUPPORT select FORCE_AM1_SOCKET_SUPPORT
select GFXUMA select GFXUMA

4
src/mainboard/biostar/am1ml/Kconfig.name
View File

@ -1,2 +1,2 @@
#config BOARD_BIOSTAR_AM1ML config BOARD_BIOSTAR_AM1ML
# bool"AM1ML" bool"AM1ML"

2
src/mainboard/biostar/am1ml/Makefile.inc
View File

@ -13,6 +13,8 @@
# GNU General Public License for more details. # GNU General Public License for more details.
# #
bootblock-y += bootblock.c
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c romstage-y += OemCustomize.c

70
src/mainboard/biostar/am1ml/romstage.c → src/mainboard/biostar/am1ml/bootblock.c
View File

@ -1,26 +1,19 @@
/* /*
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com>
*
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License. * the Free Software Foundation; version 2 of the License.
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <arch/io.h> #include <amdblocks/acpimmio.h>
#include <bootblock_common.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <superio/ite/common/ite.h> #include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h> #include <superio/ite/it8728f/it8728f.h>
@ -28,10 +21,6 @@
#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) #define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
#define ENVC_DEV PNP_DEV(0x2e, IT8728F_EC) #define ENVC_DEV PNP_DEV(0x2e, IT8728F_EC)
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
static void ite_evc_conf(pnp_devfn_t dev) static void ite_evc_conf(pnp_devfn_t dev)
{ {
pnp_enter_conf_state(dev); pnp_enter_conf_state(dev);
@ -70,28 +59,13 @@ static void ite_gpio_conf(pnp_devfn_t dev)
pnp_exit_conf_state(dev); pnp_exit_conf_state(dev);
} }
void board_BeforeAgesa(struct sysinfo *cb) void bootblock_mainboard_early_init(void)
{ {
u32 val, t32; volatile u32 *addr32;
u8 byte; u32 t32;
pci_devfn_t dev;
u32 *addr32;
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA pm_write8(0xea, 0x1);
* even though the register is not documented in the Kabini BKDG.
* Otherwise the serial output is bad code.
*/
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
/* Set LPC decode enables. */
pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev2, 0x44, 0xff03ffd5);
/* Enable the AcpiMmio space */
outb(0x24, 0xcd6);
outb(0x1, 0xcd7);
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
addr32 = (u32 *)0xfed80e28; addr32 = (u32 *)0xfed80e28;
@ -105,35 +79,11 @@ void board_BeforeAgesa(struct sysinfo *cb)
t32 &= 0xffffbffb; t32 &= 0xffffbffb;
*addr32 = t32; *addr32 = t32;
/* enable SIO LPC decode */ /* Configure SIO as made under vendor BIOS */
dev = PCI_DEV(0, 0x14, 3);
byte = pci_read_config8(dev, 0x48);
byte |= 3; /* 2e, 2f */
pci_write_config8(dev, 0x48, byte);
/* enable serial decode */
byte = pci_read_config8(dev, 0x44);
byte |= (1 << 6); /* 0x3f8 */
pci_write_config8(dev, 0x44, byte);
/* This functions configure SIO as it been done under vendor bios */
printk(BIOS_DEBUG, "ITE CONFIG ENVC\n");
ite_evc_conf(ENVC_DEV); ite_evc_conf(ENVC_DEV);
printk(BIOS_DEBUG, "ITE CONFIG GPIO\n");
ite_gpio_conf(GPIO_DEV); ite_gpio_conf(GPIO_DEV);
printk(BIOS_DEBUG, "ITE CONFIG DONE\n");
/* Enable serial output on it8728f */
ite_kill_watchdog(GPIO_DEV); ite_kill_watchdog(GPIO_DEV);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
int i;
for (i = 0; i < 200000; i++)
val = inb(0xcd6);
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
post_code(0x50);
} }