biostar/am1ml: Switch away from ROMCC_BOOTBLOCK
Switching was done by moving a SIO configuration and a clocks setup from 'romstage.c' to 'bootblock.c' TEST=Boots into Ubuntu Linux 16.04.6 without a problem. Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f Signed-off-by: Sergej Ivanov <getinaks@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Sergej Ivanov
Kyösti Mälkki
parent
9c6e9c684f
commit
fc749b23ef
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@ -20,9 +20,6 @@ choice
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source "src/mainboard/biostar/*/Kconfig.name"
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config BIOSTAR_BOARDS_DISABLED
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bool "Boards from vendor are disabled"
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endchoice
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source "src/mainboard/biostar/*/Kconfig"
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@ -14,15 +14,11 @@
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# GNU General Public License for more details.
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#
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config BOARD_BIOSTAR_AM1ML
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def_bool n
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if BOARD_BIOSTAR_AM1ML
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_4096
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#select ROMCC_BOOTBLOCK
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select CPU_AMD_AGESA_FAMILY16_KB
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select FORCE_AM1_SOCKET_SUPPORT
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select GFXUMA
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@ -1,2 +1,2 @@
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#config BOARD_BIOSTAR_AM1ML
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# bool"AM1ML"
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config BOARD_BIOSTAR_AM1ML
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bool"AM1ML"
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@ -13,6 +13,8 @@
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# GNU General Public License for more details.
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#
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bootblock-y += bootblock.c
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romstage-y += buildOpts.c
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romstage-y += BiosCallOuts.c
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romstage-y += OemCustomize.c
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@ -1,9 +1,6 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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* Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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@ -14,13 +11,9 @@
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <amdblocks/acpimmio.h>
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#include <bootblock_common.h>
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#include <device/pnp_ops.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <southbridge/amd/common/amd_defs.h>
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#include <southbridge/amd/agesa/hudson/hudson.h>
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#include <superio/ite/common/ite.h>
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#include <superio/ite/it8728f/it8728f.h>
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@ -28,10 +21,6 @@
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#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
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#define ENVC_DEV PNP_DEV(0x2e, IT8728F_EC)
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#define MMIO_NON_POSTED_START 0xfed00000
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#define MMIO_NON_POSTED_END 0xfedfffff
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#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
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static void ite_evc_conf(pnp_devfn_t dev)
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{
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pnp_enter_conf_state(dev);
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@ -70,28 +59,13 @@ static void ite_gpio_conf(pnp_devfn_t dev)
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pnp_exit_conf_state(dev);
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}
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void board_BeforeAgesa(struct sysinfo *cb)
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void bootblock_mainboard_early_init(void)
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{
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u32 val, t32;
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u8 byte;
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pci_devfn_t dev;
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u32 *addr32;
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volatile u32 *addr32;
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u32 t32;
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/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
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* even though the register is not documented in the Kabini BKDG.
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* Otherwise the serial output is bad code.
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*/
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outb(0xD2, 0xcd6);
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outb(0x00, 0xcd7);
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/* Set LPC decode enables. */
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pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3);
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pci_write_config32(dev2, 0x44, 0xff03ffd5);
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/* Enable the AcpiMmio space */
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outb(0x24, 0xcd6);
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outb(0x1, 0xcd7);
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/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
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pm_write8(0xea, 0x1);
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/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
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addr32 = (u32 *)0xfed80e28;
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@ -105,35 +79,11 @@ void board_BeforeAgesa(struct sysinfo *cb)
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t32 &= 0xffffbffb;
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*addr32 = t32;
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/* enable SIO LPC decode */
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dev = PCI_DEV(0, 0x14, 3);
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byte = pci_read_config8(dev, 0x48);
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byte |= 3; /* 2e, 2f */
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pci_write_config8(dev, 0x48, byte);
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/* enable serial decode */
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byte = pci_read_config8(dev, 0x44);
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byte |= (1 << 6); /* 0x3f8 */
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pci_write_config8(dev, 0x44, byte);
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/* This functions configure SIO as it been done under vendor bios */
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printk(BIOS_DEBUG, "ITE CONFIG ENVC\n");
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/* Configure SIO as made under vendor BIOS */
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ite_evc_conf(ENVC_DEV);
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printk(BIOS_DEBUG, "ITE CONFIG GPIO\n");
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ite_gpio_conf(GPIO_DEV);
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printk(BIOS_DEBUG, "ITE CONFIG DONE\n");
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/* Enable serial output on it8728f */
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ite_kill_watchdog(GPIO_DEV);
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ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
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int i;
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for (i = 0; i < 200000; i++)
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val = inb(0xcd6);
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outb(0xEA, 0xCD6);
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outb(0x1, 0xcd7);
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post_code(0x50);
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}
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