From fc7a40fad988102711f914b45843f80ca9b090a5 Mon Sep 17 00:00:00 2001 From: Kenneth Chan Date: Thu, 6 Jan 2022 10:22:34 +0800 Subject: [PATCH] mb/google/guybrush/var/dewatt: update USB3 settings for passing SI Update tx/rx term control to 3 for passing USB3 port 0/1 SI. b:199468920 TEST= emerge-guybrush coreboot; build and pass USB3 SI. Signed-off-by: Kenneth Chan Change-Id: I637207d7c657f6dd71d70694f9a5fb35f8294b64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60809 Tested-by: build bot (Jenkins) Reviewed-by: Rob Barnes --- .../guybrush/variants/dewatt/overridetree.cb | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb index 9a9e760de6..e14ae4a575 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb @@ -18,7 +18,7 @@ chip soc/amd/cezanne register "telemetry_vddcrsocfull_scale_current_mA" = "31481" #mA register "telemetry_vddcrsocoffset" = "193" - #USB 2.0 phy config + #USB 2/3 phy config register "usb_phy" = "{ /* Left USB C0 Port */ .Usb2PhyPort[0] = { @@ -56,6 +56,20 @@ chip soc/amd/cezanne .txhsxvtune = 3, .txrestune = 1, }, + /* Left USB C0 Port */ + .Usb3PhyPort[0] = { + .tx_term_ctrl=3, + .rx_term_ctrl=3, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, + /* Left USB A0 Port */ + .Usb3PhyPort[1] = { + .tx_term_ctrl=3, + .rx_term_ctrl=3, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, }" # general purpose PCIe clock output configuration