Documentation: Add Asus P2B-LS
Change-Id: Ib885c4dd8472ed2b0a61c548f6ef652979a33153 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Documentation/mainboard/asus/p2b-ls.md
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# ASUS P2B-LS
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This page describes how to run coreboot on the ASUS P2B-LS mainboard.
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## Variants
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- P2B-LS
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- P2B-L (Same circuit board with SCSI components omitted)
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- P2B-S (Same circuit board with ethernet components omitted)
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## Flashing coreboot
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```eval_rst
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+---------------------+---------------------------+
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| Type | Value |
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+=====================+===========================+
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| Model | SST 39SF020A (or similar) |
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+---------------------+---------------------------+
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| Protocol | Parallel |
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+---------------------+---------------------------+
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| Size | 256 KiB |
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+---------------------+---------------------------+
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| Package | DIP-32 |
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+---------------------+---------------------------+
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| Socketed | yes |
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+---------------------+---------------------------+
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| Write protection | no |
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+---------------------+---------------------------+
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| Dual BIOS feature | no |
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+---------------------+---------------------------+
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| Internal flashing | yes |
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+---------------------+---------------------------+
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```
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[flashrom] works out of the box since 0.9.2.
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Because of deficiency in vendor firmware, user needs to override the laptop
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warning as prompted. Once coreboot is in place there will be no further issue.
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### CPU microcode considerations
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By default, this board includes microcode updates for 5 families of Intel CPUs
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because of the wide variety of CPUs the board supports, directly or with an
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adapter. These take up a third of the total flash space leaving only 20kB free
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in the final cbfs image. It may be necessary to build a custom microcode update
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file by manually concatenating files in 3rdparty/intel-microcode/intel-ucode
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for only CPU models that the board will actually be run with.
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## Working
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- Slot 1 and Socket 370 CPUs and their L1/L2 caches
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- PS/2 keyboard with SeaBIOS (See [Known issues])
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- IDE hard drives
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- Ethernet (-LS, -L; Intel 82558)
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- SCSI (-LS, -S; Adaptec AIC7890)
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- USB
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- ISA add-on cards
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- PCI add-on cards
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- AGP graphics card
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- Floppy
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- Serial ports 1 and 2
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- Reboot
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- Soft off
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## Known issues
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- PS/2 keyboard may not be usable until Linux has completely booted.
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With SeaBIOS as payload, setting keyboard initialization timeout to
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500ms may fix the issue.
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- i440BX does not support 256Mbit RAM modules. If installed, coreboot
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will attempt to initialize them at half their capacity anyway
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whereas vendor firmware will not boot at all.
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- ECC memory can be used, but ECC support is still pending.
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- Termination is enabled for all SCSI ports (if equipped). Support to
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disable termination is pending. Note that the SCSI-68 port is
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always terminated, even with vendor firmware.
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## Untested
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- Parallel port
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- EDO memory
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- Infrared
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- PC speaker
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## Not working
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- S3 suspend to RAM
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| Northbridge | :doc:`../../northbridge/intel/i440bx/index` |
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+------------------+--------------------------------------------------+
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| Southbridge | i82371eb |
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+------------------+--------------------------------------------------+
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| CPU | P6 family for Slot 1 and Socket 370 |
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| | (all models from model_63x to model_6bx) |
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+------------------+--------------------------------------------------+
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| Super I/O | winbond/w83977tf |
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+------------------+--------------------------------------------------+
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```
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## Extra resources
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[flashrom]: https://flashrom.org/Flashrom
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