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nb/intel/sandybridge: Refactor get_mem_min_tck 

It is not necessary to pass its value around various function calls.
Move it closer to where it is actually used, so as to make it static.
Also, use config_of_soc and flip the branches of the first conditional.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: I5c49c943c87218d4d40d3168bd8b7b900b0ec2e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39851
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-03-24 11:12:09 +01:00
parent 64ba44f7fb
commit fc9302465b
4 changed files with 82 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/northbridge/intel/sandybridge/raminit.c
View File

@ -226,11 +226,10 @@ static void save_timings(ramctr_timing *ctrl)
mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl));
}
static void reinit_ctrl(ramctr_timing *ctrl, int min_tck, const u32 cpuid)
static void reinit_ctrl(ramctr_timing *ctrl, const u32 cpuid)
{
/* Reset internal state */
memset(ctrl, 0, sizeof(*ctrl));
ctrl->tCK = min_tck;
/* Get architecture */
ctrl->cpu = cpuid;
@ -243,7 +242,7 @@ static void reinit_ctrl(ramctr_timing *ctrl, int min_tck, const u32 cpuid)
ctrl->ecc_forced ? "yes" : "no");
}
static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid)
static void init_dram_ddr3(int s3resume, const u32 cpuid)
{
int me_uma_size, cbmem_was_inited, fast_boot, err;
ramctr_timing ctrl;
@ -329,7 +328,7 @@ static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid)
}
if (!fast_boot) {
/* Reset internal state */
reinit_ctrl(&ctrl, min_tck, cpuid);
reinit_ctrl(&ctrl, cpuid);
printk(BIOS_INFO, "ECC RAM %s.\n", ctrl.ecc_forced ? "required" :
ctrl.ecc_supported ? "supported" : "unsupported");
@ -348,7 +347,7 @@ static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid)
printram("Disable failing channel.\n");
/* Reset internal state */
reinit_ctrl(&ctrl, min_tck, cpuid);
reinit_ctrl(&ctrl, cpuid);
/* Reset DDR3 frequency */
dram_find_spds_ddr3(spds, &ctrl);
@ -398,5 +397,5 @@ void perform_raminit(int s3resume)
timestamp_add_now(TS_BEFORE_INITRAM);
init_dram_ddr3(get_mem_min_tck(), s3resume, cpu_get_cpuid());
init_dram_ddr3(s3resume, cpu_get_cpuid());
}

69
src/northbridge/intel/sandybridge/raminit_common.c
View File

@ -358,75 +358,6 @@ void dram_zones(ramctr_timing *ctrl, int training)
}
}
#define DEFAULT_TCK TCK_800MHZ
unsigned int get_mem_min_tck(void)
{
u32 reg32;
u8 rev;
const struct device *dev;
const struct northbridge_intel_sandybridge_config *cfg = NULL;
dev = pcidev_path_on_root(PCI_DEVFN(0, 0));
if (dev)
cfg = dev->chip_info;
/* If this is zero, it just means devicetree.cb didn't set it */
if (!cfg || cfg->max_mem_clock_mhz == 0) {
if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))
return TCK_1333MHZ;
rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID);
if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
/* Read Capabilities A Register DMFC bits */
reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A);
reg32 &= 0x7;
switch (reg32) {
case 7: return TCK_533MHZ;
case 6: return TCK_666MHZ;
case 5: return TCK_800MHZ;
/* Reserved */
default:
break;
}
} else {
/* Read Capabilities B Register DMFC bits */
reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B);
reg32 = (reg32 >> 4) & 0x7;
switch (reg32) {
case 7: return TCK_533MHZ;
case 6: return TCK_666MHZ;
case 5: return TCK_800MHZ;
case 4: return TCK_933MHZ;
case 3: return TCK_1066MHZ;
case 2: return TCK_1200MHZ;
case 1: return TCK_1333MHZ;
/* Reserved */
default:
break;
}
}
return DEFAULT_TCK;
} else {
if (cfg->max_mem_clock_mhz >= 1066)
return TCK_1066MHZ;
else if (cfg->max_mem_clock_mhz >= 933)
return TCK_933MHZ;
else if (cfg->max_mem_clock_mhz >= 800)
return TCK_800MHZ;
else if (cfg->max_mem_clock_mhz >= 666)
return TCK_666MHZ;
else if (cfg->max_mem_clock_mhz >= 533)
return TCK_533MHZ;
else
return TCK_400MHZ;
}
}
#define DEFAULT_PCI_MMIO_SIZE 2048
static unsigned int get_mmio_size(void)

1
src/northbridge/intel/sandybridge/raminit_common.h
View File

@ -174,7 +174,6 @@ void dram_timing_regs(ramctr_timing *ctrl);
void dram_dimm_mapping(ramctr_timing *ctrl);
void dram_dimm_set_mapping(ramctr_timing *ctrl, int training);
void dram_zones(ramctr_timing *ctrl, int training);
unsigned int get_mem_min_tck(void);
void dram_memorymap(ramctr_timing *ctrl, int me_uma_size);
void dram_jedecreset(ramctr_timing *ctrl);
int read_training(ramctr_timing *ctrl);

77
src/northbridge/intel/sandybridge/raminit_native.c
View File

@ -5,7 +5,10 @@
#include <console/console.h>
#include <console/usb.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/chip.h>
#include "raminit_native.h"
#include "raminit_common.h"
#include "raminit_tables.h"
@ -174,6 +177,78 @@ static void normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support)
}
}
#define DEFAULT_TCK TCK_800MHZ
static unsigned int get_mem_min_tck(void)
{
u32 reg32;
u8 rev;
const struct northbridge_intel_sandybridge_config *cfg = NULL;
/* Actually, config of MCH or Host Bridge */
cfg = config_of_soc();
/* If non-zero, it was set in the devicetree */
if (cfg->max_mem_clock_mhz) {
if (cfg->max_mem_clock_mhz >= 1066)
return TCK_1066MHZ;
else if (cfg->max_mem_clock_mhz >= 933)
return TCK_933MHZ;
else if (cfg->max_mem_clock_mhz >= 800)
return TCK_800MHZ;
else if (cfg->max_mem_clock_mhz >= 666)
return TCK_666MHZ;
else if (cfg->max_mem_clock_mhz >= 533)
return TCK_533MHZ;
else
return TCK_400MHZ;
}
if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))
return TCK_1333MHZ;
rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID);
if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
/* Read Capabilities A Register DMFC bits */
reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A);
reg32 &= 0x7;
switch (reg32) {
case 7: return TCK_533MHZ;
case 6: return TCK_666MHZ;
case 5: return TCK_800MHZ;
/* Reserved */
default:
break;
}
} else {
/* Read Capabilities B Register DMFC bits */
reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B);
reg32 = (reg32 >> 4) & 0x7;
switch (reg32) {
case 7: return TCK_533MHZ;
case 6: return TCK_666MHZ;
case 5: return TCK_800MHZ;
case 4: return TCK_933MHZ;
case 3: return TCK_1066MHZ;
case 2: return TCK_1200MHZ;
case 1: return TCK_1333MHZ;
/* Reserved */
default:
break;
}
}
return DEFAULT_TCK;
}
static void find_cas_tck(ramctr_timing *ctrl)
{
u8 val;
@ -188,6 +263,8 @@ static void find_cas_tck(ramctr_timing *ctrl)
printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support);
ctrl->tCK = get_mem_min_tck();
/* Find CAS latency */
while (1) {
/*