diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 1d4bd5fa5a..64c13ce22e 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -231,6 +231,15 @@ struct soc_intel_tigerlake_config {
 	uint8_t TcssXhciEn;
 	uint8_t TcssXdciEn;
 
+	/*
+	 * SOC Aux orientation override:
+	 * This is a bitfield that corresponds to up to 4 TCSS ports on TGL.
+	 * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC.
+	 * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines
+	 * on the motherboard.
+	 */
+	uint16_t TcssAuxOri;
+
 	/*
 	 * Override GPIO PM configuration:
 	 * 0: Use FSP default GPIO PM program,
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index a8be407d23..8e9787b12b 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -104,6 +104,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	else
 		params->PeiGraphicsPeimInit = 0;
 
+	params->TcssAuxOri = config->TcssAuxOri;
 	for (i = 0; i < 8; i++)
 		params->IomTypeCPortPadCfg[i] = 0x09000000;