diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 9d10cac41b..1123d53734 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -72,6 +72,7 @@ chip soc/intel/cannonlake
 
 	# Enable Root port 9(x4) for NVMe.
 	register "PcieRpEnable[8]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
 	# RP 9 uses CLK SRC 1
 	register "PcieClkSrcUsage[1]" = "8"
 	# ClkReq-to-ClkSrc mapping for CLK SRC 1
@@ -79,6 +80,7 @@ chip soc/intel/cannonlake
 
 	# PCIe port 14 for M.2 E-key WLAN
 	register "PcieRpEnable[13]" = "1"
+	register "PcieRpLtrEnable[13]" = "1"
 	# RP 14 uses CLK SRC 3
 	register "PcieClkSrcUsage[3]" = "13"
 	register "PcieClkSrcClkReq[3]" = "3"