From fca7c4d614eeee1b040cfeba37599b32d0ad55f1 Mon Sep 17 00:00:00 2001
From: Furquan Shaikh <furquan@google.com>
Date: Sat, 1 Jun 2019 14:44:56 -0700
Subject: [PATCH] mb/google/hatch: Enable LTR for PCIe ports

Enable LTR for NVMe and WiFi PCIe ports so that they can use ASPM L1.2

BUG=b:134195632
TEST=Verified L1 substate with lspci on hatch:
Before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+
After: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+

Change-Id: I7fce60897b78dde12747ac7fb857c988d16118ab
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33161
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 9d10cac41b..1123d53734 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -72,6 +72,7 @@ chip soc/intel/cannonlake
 
 	# Enable Root port 9(x4) for NVMe.
 	register "PcieRpEnable[8]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
 	# RP 9 uses CLK SRC 1
 	register "PcieClkSrcUsage[1]" = "8"
 	# ClkReq-to-ClkSrc mapping for CLK SRC 1
@@ -79,6 +80,7 @@ chip soc/intel/cannonlake
 
 	# PCIe port 14 for M.2 E-key WLAN
 	register "PcieRpEnable[13]" = "1"
+	register "PcieRpLtrEnable[13]" = "1"
 	# RP 14 uses CLK SRC 3
 	register "PcieClkSrcUsage[3]" = "13"
 	register "PcieClkSrcClkReq[3]" = "3"