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mb/google/brya/var/taeko: disabled autonomous GPIO power management 

Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M

BUG=b:205315500
TEST=emerge-brya coreboot and test that DUT can boot to OS.

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib26797fa2d4d0b1a6eb28c5d79b9ac0a6054abd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Joey Peng 2021-11-16 08:58:00 +08:00 committed by Tim Wawrzynczak
parent 85d9f47014
commit fcb267a81d
1 changed files with 10 additions and 0 deletions
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10
src/mainboard/google/brya/variants/taeko/overridetree.cb
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@ -41,6 +41,16 @@ fw_config
end end
end end
chip soc/intel/alderlake chip soc/intel/alderlake
# This disabled autonomous GPIO power management, otherwise
# old cr50 FW only supports short pulses; need to clarify
# the minimum PCH IRQ pulse width with Intel, b/180111628
register "gpio_override_pm" = "1"
register "gpio_pm[COMM_0]" = "0"
register "gpio_pm[COMM_1]" = "0"
register "gpio_pm[COMM_2]" = "0"
register "gpio_pm[COMM_3]" = "0"
register "gpio_pm[COMM_4]" = "0"
register "gpio_pm[COMM_5]" = "0"
register "ext_fivr_settings" = "{ register "ext_fivr_settings" = "{
.configure_ext_fivr = 1, .configure_ext_fivr = 1,
.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,