From fcc26f54a0dc5db0845946b20e1a03b77a8877ae Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 25 Oct 2020 13:32:46 +0100
Subject: [PATCH] soc/intel/broadwell/pch/acpi: Add PCIe register offsets

These are present in common southbridge ACPI code, and also exist on
Broadwell. Thus, add the definitions to align with common ACPI code.

Change-Id: Ib0ad9da80920fe7c70986e541c50f6adccb49d0c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46761
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/broadwell/pch/acpi/pcie_port.asl | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl
index d48ecd036e..988c8170e9 100644
--- a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl
+++ b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl
@@ -8,4 +8,10 @@ Field (RPCS, AnyAcc, NoLock, Preserve)
 	Offset (0x4c),	// Link Capabilities
 	, 24,
 	RPPN, 8,	// Root Port Number
+	Offset (0x5A),
+	, 3,
+	PDC, 1,
+	Offset (0xDF),
+	, 6,
+	HPCS, 1,
 }