- Add new cvs code to cvs
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
98e619b1ce
commit
fcd5ace00b
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@ -0,0 +1,10 @@
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dir /cpu/x86/tsc
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dir /cpu/x86/fpu
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dir /cpu/x86/mmx
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dir /cpu/x86/sse
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dir /cpu/x86/lapic
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dir /cpu/x86/cache
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dir /cpu/x86/pae
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dir /cpu/amd/mtrr
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driver model_fxx_init.o
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object apic_timer.o
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#include <stdint.h>
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#include <delay.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/lapic.h>
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void init_timer(void)
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{
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/* Set the apic timer to no interrupts and periodic mode */
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lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
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/* Set the divider to 1, no divider */
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lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
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/* Set the initial counter to 0xffffffff */
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lapic_write(LAPIC_TMICT, 0xffffffff);
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}
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void udelay(unsigned usecs)
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{
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uint32_t start, value, ticks;
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/* Calculate the number of ticks to run, our FSB runs a 200Mhz */
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ticks = usecs * 200;
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start = lapic_read(LAPIC_TMCCT);
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do {
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value = lapic_read(LAPIC_TMCCT);
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} while((start - value) < ticks);
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}
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@ -0,0 +1,369 @@
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/* Needed so the AMD K8 runs correctly. */
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/device.h>
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#include <device/chip.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/pae.h>
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#include <pc80/mc146818rtc.h>
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#include <cpu/x86/lapic.h>
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#include "../../../northbridge/amd/amdk8/amdk8.h"
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#include "../../../northbridge/amd/amdk8/cpu_rev.c"
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/mem.h>
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#include "model_fxx_msr.h"
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#define MCI_STATUS 0x401
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static inline msr_t rdmsr_amd(unsigned index)
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{
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msr_t result;
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__asm__ __volatile__ (
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"rdmsr"
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: "=a" (result.lo), "=d" (result.hi)
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: "c" (index), "D" (0x9c5a203a)
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);
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return result;
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}
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static inline void wrmsr_amd(unsigned index, msr_t msr)
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{
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__asm__ __volatile__ (
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"wrmsr"
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: /* No outputs */
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: "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a)
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);
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}
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#define MTRR_COUNT 8
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#define ZERO_CHUNK_KB 0x800UL /* 2M */
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#define TOLM_KB 0x400000UL
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struct mtrr {
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msr_t base;
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msr_t mask;
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};
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struct mtrr_state {
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struct mtrr mtrrs[MTRR_COUNT];
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msr_t top_mem, top_mem2;
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msr_t def_type;
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};
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static void save_mtrr_state(struct mtrr_state *state)
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{
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int i;
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for(i = 0; i < MTRR_COUNT; i++) {
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state->mtrrs[i].base = rdmsr(MTRRphysBase_MSR(i));
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state->mtrrs[i].mask = rdmsr(MTRRphysMask_MSR(i));
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}
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state->top_mem = rdmsr(TOP_MEM);
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state->top_mem2 = rdmsr(TOP_MEM2);
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state->def_type = rdmsr(MTRRdefType_MSR);
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}
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static void restore_mtrr_state(struct mtrr_state *state)
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{
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int i;
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disable_cache();
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for(i = 0; i < MTRR_COUNT; i++) {
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wrmsr(MTRRphysBase_MSR(i), state->mtrrs[i].base);
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wrmsr(MTRRphysMask_MSR(i), state->mtrrs[i].mask);
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}
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wrmsr(TOP_MEM, state->top_mem);
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wrmsr(TOP_MEM2, state->top_mem2);
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wrmsr(MTRRdefType_MSR, state->def_type);
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enable_cache();
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}
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#if 0
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static void print_mtrr_state(struct mtrr_state *state)
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{
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int i;
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for(i = 0; i < MTRR_COUNT; i++) {
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printk_debug("var mtrr %d: %08x%08x mask: %08x%08x\n",
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i,
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state->mtrrs[i].base.hi, state->mtrrs[i].base.lo,
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state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo);
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}
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printk_debug("top_mem: %08x%08x\n",
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state->top_mem.hi, state->top_mem.lo);
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printk_debug("top_mem2: %08x%08x\n",
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state->top_mem2.hi, state->top_mem2.lo);
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printk_debug("def_type: %08x%08x\n",
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state->def_type.hi, state->def_type.lo);
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}
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#endif
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static void set_init_ecc_mtrrs(void)
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{
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msr_t msr;
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int i;
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disable_cache();
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/* First clear all of the msrs to be safe */
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for(i = 0; i < MTRR_COUNT; i++) {
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msr_t zero;
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zero.lo = zero.hi = 0;
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wrmsr(MTRRphysBase_MSR(i), zero);
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wrmsr(MTRRphysMask_MSR(i), zero);
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}
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/* Write back cache the first 1MB */
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msr.hi = 0x00000000;
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msr.lo = 0x00000000 | MTRR_TYPE_WRBACK;
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wrmsr(MTRRphysBase_MSR(0), msr);
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msr.hi = 0x000000ff;
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msr.lo = ~((CONFIG_LB_MEM_TOPK << 10) - 1) | 0x800;
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wrmsr(MTRRphysMask_MSR(0), msr);
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/* Set the default type to write combining */
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msr.hi = 0x00000000;
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msr.lo = 0xc00 | MTRR_TYPE_WRCOMB;
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wrmsr(MTRRdefType_MSR, msr);
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/* Set TOP_MEM to 4G */
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msr.hi = 0x00000001;
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msr.lo = 0x00000000;
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wrmsr(TOP_MEM, msr);
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enable_cache();
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}
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static void init_ecc_memory(void)
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{
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unsigned long startk, begink, endk;
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unsigned long basek;
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struct mtrr_state mtrr_state;
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device_t f1_dev, f2_dev, f3_dev;
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int node_id;
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int enable_scrubbing;
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uint32_t dcl;
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/* For now there is a 1-1 mapping between node_id and cpu_id */
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node_id = lapicid();
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f1_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 1));
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if (!f1_dev) {
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die("Cannot find cpu function 1\n");
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}
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f2_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 2));
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if (!f2_dev) {
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die("Cannot find cpu function 2\n");
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}
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f3_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 3));
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if (!f3_dev) {
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die("Cannot find cpu function 3\n");
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}
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/* See if we scrubbing should be enabled */
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enable_scrubbing = 1;
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get_option(&enable_scrubbing, "hw_scrubber");
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/* Enable cache scrubbing at the lowest possible rate */
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if (enable_scrubbing) {
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pci_write_config32(f3_dev, SCRUB_CONTROL,
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(SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_NONE << 0));
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} else {
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pci_write_config32(f3_dev, SCRUB_CONTROL,
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(SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));
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printk_debug("Scrubbing Disabled\n");
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}
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/* If ecc support is not enabled don't touch memory */
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dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
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if (!(dcl & DCL_DimmEccEn)) {
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return;
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}
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startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
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endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
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/* Don't start too early */
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begink = startk;
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if (begink < CONFIG_LB_MEM_TOPK) {
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begink = CONFIG_LB_MEM_TOPK;
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}
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printk_debug("Clearing memory %uK - %uK: ", startk, endk);
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/* Save the normal state */
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save_mtrr_state(&mtrr_state);
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/* Switch to the init ecc state */
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set_init_ecc_mtrrs();
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disable_lapic();
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/* Walk through 2M chunks and zero them */
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for(basek = begink; basek < endk; basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) {
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unsigned long limitk;
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unsigned long size;
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void *addr;
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/* Report every 64M */
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if ((basek % (64*1024)) == 0) {
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/* Restore the normal state */
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map_2M_page(0);
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restore_mtrr_state(&mtrr_state);
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enable_lapic();
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/* Print a status message */
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printk_debug("%c", (basek >= TOLM_KB)?'+':'-');
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/* Return to the initialization state */
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set_init_ecc_mtrrs();
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disable_lapic();
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}
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limitk = (basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1);
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if (limitk > endk) {
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limitk = endk;
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}
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size = (limitk - basek) << 10;
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addr = map_2M_page(basek >> 11);
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addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
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if (addr == MAPPING_ERROR) {
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continue;
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}
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/* clear memory 2M (limitk - basek) */
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clear_memory(addr, size);
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}
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/* Restore the normal state */
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map_2M_page(0);
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restore_mtrr_state(&mtrr_state);
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enable_lapic();
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/* Set the scrub base address registers */
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pci_write_config32(f3_dev, SCRUB_ADDR_LOW, startk << 10);
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pci_write_config32(f3_dev, SCRUB_ADDR_HIGH, startk >> 22);
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/* Enable the scrubber? */
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if (enable_scrubbing) {
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/* Enable scrubbing at the lowest possible rate */
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pci_write_config32(f3_dev, SCRUB_CONTROL,
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(SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_84ms << 0));
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}
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printk_debug(" done\n");
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}
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static inline void k8_errata(void)
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{
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msr_t msr;
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if (is_cpu_pre_c0()) {
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/* Erratum 63... */
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msr = rdmsr(HWCR_MSR);
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msr.lo |= (1 << 6);
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wrmsr(HWCR_MSR, msr);
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/* Erratum 69... */
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msr = rdmsr_amd(BU_CFG_MSR);
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msr.hi |= (1 << (45 - 32));
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wrmsr_amd(BU_CFG_MSR, msr);
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/* Erratum 81... */
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msr = rdmsr_amd(DC_CFG_MSR);
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msr.lo |= (1 << 10);
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wrmsr_amd(DC_CFG_MSR, msr);
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}
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/* I can't touch this msr on early buggy cpus */
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if (!is_cpu_pre_b3()) {
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/* Erratum 89 ... */
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msr = rdmsr(NB_CFG_MSR);
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msr.lo |= 1 << 3;
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if (!is_cpu_pre_c0()) {
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/* Erratum 86 Disable data masking on C0 and
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* later processor revs.
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* FIXME this is only needed if ECC is enabled.
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*/
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msr.hi |= 1 << (36 - 32);
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}
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wrmsr(NB_CFG_MSR, msr);
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}
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/* Erratum 97 ... */
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if (!is_cpu_pre_c0()) {
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msr = rdmsr_amd(DC_CFG_MSR);
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msr.lo |= 1 << 3;
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wrmsr_amd(DC_CFG_MSR, msr);
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}
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/* Erratum 94 ... */
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msr = rdmsr_amd(IC_CFG_MSR);
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msr.lo |= 1 << 11;
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wrmsr_amd(IC_CFG_MSR, msr);
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/* Erratum 91 prefetch miss is handled in the kernel */
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}
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void model_fxx_init(device_t dev)
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{
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unsigned long mmio_basek, tomk;
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unsigned long i;
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msr_t msr;
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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amd_setup_mtrrs();
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x86_mtrr_check();
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disable_cache();
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/* zero the machine check error status registers */
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msr.lo = 0;
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msr.hi = 0;
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for(i=0; i<5; i++) {
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wrmsr(MCI_STATUS + (i*4),msr);
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}
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k8_errata();
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enable_cache();
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/* Is this a bad location? In particular can another node prefecth
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* data from this node before we have initialized it?
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*/
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init_ecc_memory();
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/* Enable the local cpu apics */
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setup_lapic();
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}
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static struct device_operations cpu_dev_ops = {
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.init = model_fxx_init,
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};
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, 0xf50 }, /* B3 */
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{ X86_VENDOR_AMD, 0xf51 }, /* SH7-B3 */
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{ X86_VENDOR_AMD, 0xf58 }, /* SH7-C0 */
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{ X86_VENDOR_AMD, 0xf48 },
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#if 1
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{ X86_VENDOR_AMD, 0xf5A }, /* SH7-CG */
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{ X86_VENDOR_AMD, 0xf4A },
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{ X86_VENDOR_AMD, 0xf7A },
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{ X86_VENDOR_AMD, 0xfc0 }, /* DH7-CG */
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{ X86_VENDOR_AMD, 0xfe0 },
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{ X86_VENDOR_AMD, 0xff0 },
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{ X86_VENDOR_AMD, 0xf82 }, /* CH7-CG */
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{ X86_VENDOR_AMD, 0xfb2 },
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#endif
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{ 0, 0 },
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};
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static struct cpu_driver model_fxx __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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@ -0,0 +1,10 @@
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#ifndef CPU_AMD_MODEL_FXX_MSR_H
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#define CPU_AMD_MODEL_FXX_MSR_H
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#define HWCR_MSR 0xC0010015
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#define NB_CFG_MSR 0xC001001f
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#define IC_CFG_MSR 0xC0011021
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#define DC_CFG_MSR 0xC0011022
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#define BU_CFG_MSR 0xC0011023
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#endif /* CPU_AMD_MODEL_FXX_MSR_H */
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@ -0,0 +1,2 @@
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dir /cpu/x86/mtrr
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object amd_mtrr.c
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@ -0,0 +1,46 @@
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#ifndef AMD_EARLYMTRR_C
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#define AMD_EARLYMTRR_C
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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#include "cpu/x86/mtrr/earlymtrr.c"
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static void amd_early_mtrr_init(void)
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{
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static const unsigned long mtrr_msrs[] = {
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/* fixed mtrr */
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0x250, 0x258, 0x259,
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0x268, 0x269, 0x26A,
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0x26B, 0x26C, 0x26D,
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0x26E, 0x26F,
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/* var mtrr */
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0x200, 0x201, 0x202, 0x203,
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0x204, 0x205, 0x206, 0x207,
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0x208, 0x209, 0x20A, 0x20B,
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0x20C, 0x20D, 0x20E, 0x20F,
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/* var iorr */
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0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019,
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/* mem top */
|
||||
0xC001001A, 0xC001001D,
|
||||
/* NULL end of table */
|
||||
0
|
||||
};
|
||||
msr_t msr;
|
||||
|
||||
disable_cache();
|
||||
do_early_mtrr_init(mtrr_msrs);
|
||||
|
||||
/* Enable memory access for 0 - 1MB using top_mem */
|
||||
msr.hi = 0;
|
||||
msr.lo = (((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK);
|
||||
wrmsr(TOP_MEM, msr);
|
||||
|
||||
/* Enable the MTRRs in SYSCFG */
|
||||
msr = rdmsr(SYSCFG_MSR);
|
||||
msr.lo |= SYSCFG_MSR_MtrrVarDramEn;
|
||||
wrmsr(SYSCFG_MSR, msr);
|
||||
|
||||
enable_cache();
|
||||
}
|
||||
|
||||
#endif /* AMD_EARLYMTRR_C */
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
|
||||
static unsigned long resk(uint64_t value)
|
||||
{
|
||||
unsigned long resultk;
|
||||
if (value < (1ULL << 42)) {
|
||||
resultk = value >> 10;
|
||||
}
|
||||
else {
|
||||
resultk = 0xffffffff;
|
||||
}
|
||||
return resultk;
|
||||
}
|
||||
|
||||
void amd_setup_mtrrs(void)
|
||||
{
|
||||
unsigned long mmio_basek, tomk;
|
||||
unsigned long i;
|
||||
device_t dev;
|
||||
msr_t msr;
|
||||
|
||||
x86_setup_mtrrs();
|
||||
|
||||
/* Except for the PCI MMIO hole just before 4GB there are no
|
||||
* significant holes in the address space, so just account
|
||||
* for those two and move on.
|
||||
*/
|
||||
mmio_basek = tomk = 0;
|
||||
for(dev = all_devices; dev; dev = dev->next) {
|
||||
struct resource *res, *last;
|
||||
last = &dev->resource[dev->resources];
|
||||
for(res = &dev->resource[0]; res < last; res++) {
|
||||
unsigned long topk;
|
||||
if (!(res->flags & IORESOURCE_MEM) ||
|
||||
(!(res->flags & IORESOURCE_CACHEABLE))) {
|
||||
continue;
|
||||
}
|
||||
topk = resk(res->base + res->size);
|
||||
if (tomk < topk) {
|
||||
tomk = topk;
|
||||
}
|
||||
if ((topk < 4*1024*1024) && (mmio_basek < topk)) {
|
||||
mmio_basek = topk;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (mmio_basek > tomk) {
|
||||
mmio_basek = tomk;
|
||||
}
|
||||
/* Round mmio_basek down to the nearst size that will fit in TOP_MEM */
|
||||
mmio_basek = mmio_basek & ~TOP_MEM_MASK_KB;
|
||||
/* Round tomk up to the next greater size that will fit in TOP_MEM */
|
||||
tomk = (tomk + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB;
|
||||
|
||||
disable_cache();
|
||||
|
||||
/* Setup TOP_MEM */
|
||||
msr.hi = mmio_basek >> 22;
|
||||
msr.lo = mmio_basek << 10;
|
||||
wrmsr(TOP_MEM, msr);
|
||||
|
||||
/* Setup TOP_MEM2 */
|
||||
msr.hi = tomk >> 22;
|
||||
msr.lo = tomk << 10;
|
||||
wrmsr(TOP_MEM2, msr);
|
||||
|
||||
/* zero the IORR's before we enable to prevent
|
||||
* undefined side effects.
|
||||
*/
|
||||
msr.lo = msr.hi = 0;
|
||||
for(i = IORR_FIRST; i <= IORR_LAST; i++) {
|
||||
wrmsr(i, msr);
|
||||
}
|
||||
|
||||
msr = rdmsr(SYSCFG_MSR);
|
||||
msr.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_TOM2En;
|
||||
wrmsr(SYSCFG_MSR, msr);
|
||||
|
||||
enable_cache();
|
||||
}
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
config chip.h
|
||||
object socket_940.o
|
||||
dir /cpu/amd/model_fxx
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
extern struct chip_control cpu_amd_socket_940_control;
|
||||
|
||||
struct cpu_amd_socket_940_config {
|
||||
};
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#include <device/chip.h>
|
||||
#include "chip.h"
|
||||
|
||||
|
||||
struct chip_control cpu_amd_socket_940_control = {
|
||||
.name = "socket 940",
|
||||
};
|
||||
|
|
@ -0,0 +1 @@
|
|||
object intel_sibling.o
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
#include <console/console.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <cpu/intel/hyperthreading.h>
|
||||
#include <device/device.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <smp/spinlock.h>
|
||||
|
||||
static int first_time = 1;
|
||||
static int disable_siblings = !CONFIG_LOGICAL_CPUS;
|
||||
|
||||
void intel_sibling_init(device_t cpu)
|
||||
{
|
||||
unsigned i, siblings;
|
||||
struct cpuid_result result;
|
||||
|
||||
/* On the bootstrap processor see if I want sibling cpus enabled */
|
||||
if (first_time) {
|
||||
first_time = 0;
|
||||
get_option(&disable_siblings, "hyper_threading");
|
||||
}
|
||||
result = cpuid(1);
|
||||
/* Is hypethreading supported */
|
||||
if (!(result.edx & (1 << 28))) {
|
||||
return;
|
||||
}
|
||||
/* See how many sibling cpus we have */
|
||||
siblings = (result.ebx >> 16) & 0xff;
|
||||
if (siblings < 1) {
|
||||
siblings = 1;
|
||||
}
|
||||
|
||||
#if 1
|
||||
printk_debug("CPU: %u %d siblings\n",
|
||||
cpu->path.u.apic.apic_id,
|
||||
siblings);
|
||||
#endif
|
||||
|
||||
/* See if I am a sibling cpu */
|
||||
if (cpu->path.u.apic.apic_id & (siblings -1)) {
|
||||
if (disable_siblings) {
|
||||
cpu->enabled = 0;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/* I am the primary cpu start up my siblings */
|
||||
for(i = 1; i < siblings; i++) {
|
||||
struct device_path cpu_path;
|
||||
device_t new;
|
||||
unsigned long count;
|
||||
/* Build the cpu device path */
|
||||
cpu_path.type = DEVICE_PATH_APIC;
|
||||
cpu_path.u.apic.apic_id = cpu->path.u.apic.apic_id + i;
|
||||
|
||||
|
||||
/* Allocate the new cpu device structure */
|
||||
new = alloc_dev(cpu->bus, &cpu_path);
|
||||
|
||||
if (!new) {
|
||||
continue;
|
||||
}
|
||||
|
||||
#if 1
|
||||
printk_debug("CPU: %u has sibling %u\n",
|
||||
cpu->path.u.apic.apic_id,
|
||||
new->path.u.apic.apic_id);
|
||||
#endif
|
||||
/* Start the new cpu */
|
||||
start_cpu(new);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
object microcode.o
|
||||
|
|
@ -0,0 +1,111 @@
|
|||
/* microcode.c: Microcode update for PIII and later CPUS
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/intel/microcode.h>
|
||||
|
||||
struct microcode {
|
||||
uint32_t hdrver;
|
||||
uint32_t rev;
|
||||
uint32_t date;
|
||||
uint32_t sig;
|
||||
|
||||
uint32_t cksum;
|
||||
uint32_t ldrver;
|
||||
uint32_t pf;
|
||||
|
||||
uint32_t data_size;
|
||||
uint32_t total_size;
|
||||
|
||||
uint32_t reserved[3];
|
||||
uint32_t bits[1012];
|
||||
};
|
||||
|
||||
|
||||
static inline uint32_t read_microcode_rev(void)
|
||||
{
|
||||
/* Some Intel Cpus can be very finicky about the
|
||||
* cpuid sequence used. So this is implemented in
|
||||
* assembly so that it works reliably.
|
||||
*/
|
||||
msr_t msr;
|
||||
__asm__ volatile (
|
||||
"wrmsr\n\t"
|
||||
"xorl %%eax, %%eax\n\t"
|
||||
"xorl %%edx, %%edx\n\t"
|
||||
"movl $0x8b, %%ecx\n\t"
|
||||
"wrmsr\n\t"
|
||||
"movl $0x01, %%eax\n\t"
|
||||
"cpuid\n\t"
|
||||
"movl $0x08b, %%ecx\n\t"
|
||||
"rdmsr \n\t"
|
||||
: /* outputs */
|
||||
"=a" (msr.lo), "=d" (msr.hi)
|
||||
: /* inputs */
|
||||
: /* trashed */
|
||||
"ecx"
|
||||
);
|
||||
return msr.hi;
|
||||
}
|
||||
|
||||
void intel_update_microcode(void *microcode_updates)
|
||||
{
|
||||
unsigned int eax;
|
||||
unsigned int pf, rev, sig;
|
||||
unsigned int x86_model, x86_family;
|
||||
struct microcode *m;
|
||||
char *c;
|
||||
msr_t msr;
|
||||
|
||||
/* cpuid sets msr 0x8B iff a microcode update has been loaded. */
|
||||
msr.lo = 0;
|
||||
msr.hi = 0;
|
||||
wrmsr(0x8B, msr);
|
||||
eax = cpuid_eax(1);
|
||||
msr = rdmsr(0x8B);
|
||||
rev = msr.hi;
|
||||
x86_model = (eax >>4) & 0x0f;
|
||||
x86_family = (eax >>8) & 0x0f;
|
||||
sig = eax;
|
||||
|
||||
pf = 0;
|
||||
if ((x86_model >= 5)||(x86_family>6)) {
|
||||
msr = rdmsr(0x17);
|
||||
pf = 1 << ((msr.hi >> 18) & 7);
|
||||
}
|
||||
print_debug("microcode_info: sig = 0x");
|
||||
print_debug_hex32(sig);
|
||||
print_debug(" pf=0x");
|
||||
print_debug_hex32(pf);
|
||||
print_debug(" rev = 0x");
|
||||
print_debug_hex32(rev);
|
||||
print_debug("\r\n");
|
||||
|
||||
m = microcode_updates;
|
||||
for(c = microcode_updates; m->hdrver; m = (struct microcode *)c) {
|
||||
if ((m->sig == sig) && (m->pf & pf)) {
|
||||
unsigned int new_rev;
|
||||
msr.lo = (unsigned long)(&m->bits) & 0xffffffff;
|
||||
msr.hi = 0;
|
||||
wrmsr(0x79, msr);
|
||||
|
||||
/* Read back the new microcode version */
|
||||
new_rev = read_microcode_rev();
|
||||
|
||||
print_debug("microcode updated to revision: ");
|
||||
print_debug_hex32(new_rev);
|
||||
print_debug(" from revision ");
|
||||
print_debug_hex32(rev);
|
||||
print_debug("\r\n");
|
||||
break;
|
||||
}
|
||||
if (m->total_size) {
|
||||
c += m->total_size;
|
||||
} else {
|
||||
c += 2048;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
dir /cpu/x86/tsc
|
||||
dir /cpu/x86/mtrr
|
||||
dir /cpu/x86/fpu
|
||||
dir /cpu/x86/mmx
|
||||
dir /cpu/x86/sse
|
||||
dir /cpu/x86/lapic
|
||||
dir /cpu/x86/cache
|
||||
dir /cpu/intel/microcode
|
||||
driver model_6xx_init.o
|
||||
|
|
@ -0,0 +1,140 @@
|
|||
/*
|
||||
Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
|
||||
|
||||
These microcode updates are distributed for the sole purpose of
|
||||
installation in the BIOS or Operating System of computer systems
|
||||
which include an Intel P6 family microprocessor sold or distributed
|
||||
to or by you. You are authorized to copy and install this material
|
||||
on such systems. You are not authorized to use this material for
|
||||
any other purpose.
|
||||
*/
|
||||
|
||||
/* MU16810d.inc */
|
||||
0x00000001, 0x0000000d, 0x09211999, 0x00000681,
|
||||
0x31708166, 0x00000001, 0x00000001, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x710e5240, 0xab8bc2df, 0x6e652d5a, 0xcc16718b,
|
||||
0xaa5c7d1a, 0x43ac1ba0, 0xbdf8684e, 0x82565fa7,
|
||||
0x1d108edc, 0x96d2d5a2, 0x85f783a0, 0x16e4cba1,
|
||||
0xbc311213, 0xc36c45a2, 0x443b8d2b, 0xfdc5e9ce,
|
||||
0xbb6f8637, 0x47011b8b, 0xf3898e4a, 0xb3e90f68,
|
||||
0x60af6e3a, 0xff9d3de4, 0x9fb2333c, 0x5a1a39ce,
|
||||
0xffd75d72, 0xa60cc2c0, 0x5729267c, 0xfc6d2da7,
|
||||
0x8a2c8ae7, 0x71aba5ba, 0xb639ff31, 0x8d1642b8,
|
||||
0x3aa67efc, 0x9f786473, 0xaedec560, 0x1acb694f,
|
||||
0x97582a6f, 0x8dc17ea5, 0x19636cfe, 0xb5032243,
|
||||
0xc46f764f, 0x3a5d3833, 0xf3d1a2b9, 0xc22e59be,
|
||||
0x15e0b2f3, 0xe58eff24, 0xc679600d, 0x21a3a845,
|
||||
0xc11cc921, 0xed2f5061, 0x2d4db0d1, 0xcc0cc78f,
|
||||
0x80197c08, 0x20739d8a, 0xc92ec866, 0xacef343b,
|
||||
0x47c0913a, 0xee8a69e4, 0xa7b0157e, 0x4c3607a9,
|
||||
0xcc7ff7ea, 0xb0a36667, 0x41d1bcf0, 0xf54c42d2,
|
||||
0x946c590e, 0x6da18fe9, 0xf20df0e6, 0x984a2160,
|
||||
0x479becd3, 0xfb11dd36, 0xbb816653, 0x60c605c2,
|
||||
0xf52efe8b, 0x90a9f863, 0x69654bfa, 0xf0f03f7c,
|
||||
0xbf0498d5, 0x68708d82, 0xdab94924, 0x92371217,
|
||||
0x603feed7, 0xf0ff8329, 0x9c8769df, 0x6d40ab73,
|
||||
0xd8fd132a, 0x9335543f, 0x40fd3abb, 0xf25665a0,
|
||||
0x93fe56a6, 0x682a3b24, 0xf3a0f14a, 0x97e92084,
|
||||
0x4e8736a3, 0xf322db48, 0xb65de2ad, 0x6af68474,
|
||||
0xfd6dae0d, 0x953afb0e, 0x6ef22a82, 0xfa7a3d7b,
|
||||
0xb5fe683f, 0x647579c3, 0xd184e7db, 0x99ec7c97,
|
||||
0x66486a26, 0xf08c8290, 0x94eb3fce, 0x6305e16e,
|
||||
0xd61dd210, 0x9b8bdbba, 0x41a4b4f5, 0xfca38a75,
|
||||
0x9c55c7a4, 0x6a4b1f02, 0xf277077a, 0x900e3d03,
|
||||
0x4f173146, 0xf6fbf7c8, 0xb2636cb2, 0x6329a9d7,
|
||||
0xf2697eb4, 0x90f80f6f, 0x65de6167, 0xfc6cd065,
|
||||
0xb4326188, 0x67507c3a, 0xdf3179ff, 0x91207c0b,
|
||||
0x6408ad58, 0xf7e7d2fe, 0x999af7c0, 0x6a994828,
|
||||
0xdaecedf4, 0x93cba457, 0x4d924b31, 0xf12b5ae1,
|
||||
0x9563d541, 0x65bd28f8, 0xfa87a363, 0x983adc3d,
|
||||
0x45c4f64d, 0xfae3e1ef, 0xb2eb287f, 0x6050f699,
|
||||
0xfb28cfb6, 0x999b1d45, 0x65027980, 0xf4e507d0,
|
||||
0xbbd059b7, 0x64cb2688, 0xd29dff15, 0x90927c2c,
|
||||
0x6d52471a, 0xf64fc745, 0x9e4050ff, 0x68b66e3f,
|
||||
0xd0a1dd96, 0x9fe8a5a3, 0x454c936b, 0xf926115d,
|
||||
0x9bfb60ff, 0x604049aa, 0xf3509e5c, 0x9d6cf26f,
|
||||
0x4d777c5a, 0xfd7cd5ff, 0xb15d4f35, 0x6b1aa6e3,
|
||||
0xfa279f20, 0x94916fae, 0x9b04dbcc, 0x600defd9,
|
||||
0xf2977cd8, 0x65fa64be, 0x968feaee, 0xc11681af,
|
||||
0x66568af6, 0xa539a4ee, 0xcfed5cb1, 0x108445de,
|
||||
0xa603dfdd, 0xbf5ada02, 0x14b868c5, 0xb2d3b8d2,
|
||||
0xbabf3637, 0x0c25bfbc, 0xb7a4c247, 0xf2837e05,
|
||||
0x062ce963, 0xfcb65c46, 0xc6d190e7, 0x4dfce123,
|
||||
0xcb0bf4c7, 0x8bff9d9d, 0x6794e002, 0x2879661e,
|
||||
0xa5e93199, 0x77be4be8, 0x22fe3324, 0xb943e4ef,
|
||||
0x73463d52, 0x31471050, 0xb68fd63f, 0x84cad24f,
|
||||
0x343d922b, 0x42b9ab31, 0x88ee1549, 0xe913e2ab,
|
||||
0x4a127048, 0x5057f79f, 0x636eb512, 0x42e02f9c,
|
||||
0xd3a8b863, 0x9bc40609, 0x4a18edb5, 0x86a4bdaa,
|
||||
0x91819a4b, 0x12a11e17, 0x8a6d7f21, 0xf42998d9,
|
||||
0x132b6bbd, 0xe3239feb, 0xf52519d7, 0xada08128,
|
||||
0xe6febacf, 0x44e15a80, 0xa977610a, 0xf56a8665,
|
||||
0x4693b6f0, 0xb8386320, 0xfcf7d071, 0xb8a1128d,
|
||||
0xb2a45d18, 0x075a2095, 0x98ebde53, 0xe8762eaf,
|
||||
0x838ba96f, 0x4f0239d3, 0xf295395e, 0xb3c38631,
|
||||
0x7ea7a143, 0x157a4e43, 0x46f8173f, 0xfbc18d4a,
|
||||
0xc401e17a, 0xc4620358, 0xd2ab5437, 0xa01db06f,
|
||||
0x58ce91fc, 0x850de1a3, 0x9b542dba, 0xee77f038,
|
||||
0xddd3ced6, 0xc225d2ce, 0x63a3f765, 0x3342a06c,
|
||||
0x6a780c2f, 0xfaa925b2, 0x366ebeec, 0xbcc9abea,
|
||||
0xc7b3fa4e, 0xf4f1123d, 0x5198702c, 0x3e3458b7,
|
||||
0x0b1ce9a1, 0x51b1bd7f, 0x711e791e, 0x927d8bed,
|
||||
0x91dbaea9, 0x7eefbda9, 0x7a19edd9, 0xdf7b8dce,
|
||||
0x5bb40613, 0x0b0c1e0f, 0x85b82c98, 0x18da4dc1,
|
||||
0xc5fd78ac, 0x57c1e31d, 0x4c4001b5, 0xe31d2643,
|
||||
0xa6afbf58, 0xad200e68, 0xf0114ba4, 0xd6a620f2,
|
||||
0xc753a720, 0xac9022a0, 0x28a41f01, 0x22a4ba95,
|
||||
0xc00b7531, 0x23d42795, 0xcd836a86, 0x90262708,
|
||||
0x3292cad0, 0x40022e39, 0xc1581b0a, 0xe5101550,
|
||||
0x6538096b, 0x208c549d, 0x3ce2bf88, 0xa71df38e,
|
||||
0x3dec3685, 0xca3949f1, 0x79f3ad1b, 0x3ee8b300,
|
||||
0x9d305fc6, 0x7a2e5288, 0xbe81a2f2, 0x7ada0c06,
|
||||
0x191c7f01, 0x58dfcbd1, 0xc78dee72, 0x72364226,
|
||||
0x1866de12, 0x8d22305c, 0x943a0f0e, 0xc81967ff,
|
||||
0x4d55fb0f, 0xaf199be1, 0x90bbda61, 0x4e7c234f,
|
||||
0x90cfec16, 0x9b4bcf26, 0x21622023, 0x0926f0fa,
|
||||
0x1d504377, 0xa58db427, 0x8d93ce2b, 0x90bfe900,
|
||||
0x29e67397, 0x2c1261ed, 0x4ace9474, 0xd5c60282,
|
||||
0xe53fb300, 0x8a61a0ab, 0xa7aa0918, 0x4389d7c5,
|
||||
0xd09d605c, 0x6c5bedb5, 0xd6d54c51, 0x433dea21,
|
||||
0x7ad9e677, 0x813bff76, 0x5a162c75, 0x1ee0661f,
|
||||
0x9b6c2030, 0x8e8dc989, 0xcd4bc9fc, 0x4454675b,
|
||||
0x8d583c9c, 0xe3400094, 0x116ebb83, 0xe847bc9a,
|
||||
0x2a4622dd, 0x2a901e6f, 0xd789b1c0, 0x094e2bbb,
|
||||
0x056e563f, 0x9f17e606, 0x8bc79b8d, 0xd2c535c1,
|
||||
0x06a45a27, 0x9dc56771, 0xa06649e2, 0x5ff25ac8,
|
||||
0x6554961e, 0x98e583d9, 0x38ba93da, 0xdee1de18,
|
||||
0x037cb9d5, 0x6b17f195, 0x3431faaf, 0x13860a0d,
|
||||
0x28bca10d, 0x0a54c011, 0x9957cdb6, 0x3aa1f429,
|
||||
0x9d41b7b3, 0x9aea5be2, 0x60c7ce6b, 0x4cd1c10b,
|
||||
0x24ddddcd, 0xe28412ba, 0xa03a5466, 0xa1896879,
|
||||
0x59edcb87, 0x1b241765, 0x157bf161, 0xf219f950,
|
||||
0xe86ff526, 0x262005d9, 0x11769531, 0xbca15d95,
|
||||
0x28f5ef17, 0x1f27e725, 0xc32631d2, 0x07249e61,
|
||||
0x1ba851e3, 0x4f49b577, 0xe2a1df5e, 0x826fa7ff,
|
||||
0xc34e1e2e, 0x7fe26024, 0xbc19800f, 0x0d368dc9,
|
||||
0xe03da0c6, 0xadaa4f9c, 0x9ad1e43c, 0x96f84e44,
|
||||
0x0b6cd695, 0x1bb46971, 0x942d6e5b, 0x6316170d,
|
||||
0x3164509f, 0xc6659450, 0xb2a0370a, 0xabc208e8,
|
||||
0x6d479811, 0x3684bc0e, 0x80b7b101, 0xa50b7bb5,
|
||||
0x43d21233, 0xb423559d, 0xf41dcd16, 0xdfd3c276,
|
||||
0x3e586469, 0xd9b7630a, 0xb88f9e44, 0x0cda6f4d,
|
||||
0xe5bf5844, 0x8709f788, 0xdae37da6, 0x1fb41777,
|
||||
0x1d903f69, 0x34383b69, 0xd409ae70, 0xd1c99758,
|
||||
0xdedfd7a4, 0xa4bdf018, 0xf4058202, 0x8565d66f,
|
||||
0x5365aed9, 0xfa69742e, 0x2cfbfbcf, 0x88a00b60,
|
||||
0x506c0713, 0x2866475b, 0x3e1df573, 0xb86f7feb,
|
||||
0x31d23a7f, 0xc6320e6a, 0x3ebbc2a5, 0x83a1d4ef,
|
||||
0x15169f5f, 0x42a61753, 0x893e553e, 0x4ddbc66d,
|
||||
0x7449ec1f, 0x76f65d22, 0x0622e13b, 0x32986f89,
|
||||
0x21181b4b, 0x99a80c0a, 0xd6fe00b0, 0x282c0e81,
|
||||
0x9fc1cf88, 0x919b855d, 0x618257d8, 0x82c448b8,
|
||||
0xe22537a1, 0xa90de388, 0xba73b90c, 0xd765eeb0,
|
||||
0x62b2727e, 0xa08dfe20, 0x70b3c8c5, 0x3ef04007,
|
||||
0x9f73732b, 0x2201edd7, 0xb836219c, 0xf913af7c,
|
||||
0xf50f64ca, 0x93ac107a, 0xf509f84a, 0x6f6026f6,
|
||||
0xd9bb8eac, 0x4b268cfa, 0xa65a3fa6, 0x9837cb75,
|
||||
0x784fb835, 0x2060576d, 0xb1604cae, 0xb9da4116,
|
||||
0xab320cf2, 0x60a1b501, 0x0c73fa79, 0x8d5a6f1e,
|
||||
0x57688086, 0x218e4005, 0xca054e3d, 0xc1a3c3ec,
|
||||
|
|
@ -0,0 +1,140 @@
|
|||
/*
|
||||
Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
|
||||
|
||||
These microcode updates are distributed for the sole purpose of
|
||||
installation in the BIOS or Operating System of computer systems
|
||||
which include an Intel P6 family microprocessor sold or distributed
|
||||
to or by you. You are authorized to copy and install this material
|
||||
on such systems. You are not authorized to use this material for
|
||||
any other purpose.
|
||||
*/
|
||||
|
||||
/* MU16830c.inc */
|
||||
0x00000001, 0x0000000c, 0x01102000, 0x00000683,
|
||||
0xb1605bca, 0x00000001, 0x00000001, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x7d021266, 0xd3890df1, 0x08a3a61b, 0x3c9bd396,
|
||||
0x516b77d0, 0xf119ce39, 0xd63a44b0, 0x523efada,
|
||||
0x1a0c3ed7, 0x04711f21, 0x515f945e, 0xbb5f13ba,
|
||||
0x254eabfc, 0x5bd1e959, 0x67373898, 0x61605a8f,
|
||||
0x6ea7c5a9, 0x5e64a058, 0xc0a019ee, 0x56af4cfe,
|
||||
0x1acd6406, 0x4e7eb040, 0xf2ebd7ef, 0xc659db4f,
|
||||
0xfe77108b, 0xfdceb47b, 0xf0757eb8, 0xb1622949,
|
||||
0xdceb744b, 0x19e2ad26, 0xe9c745ab, 0xb385f196,
|
||||
0x9ecc3483, 0x0a126045, 0x5320d6be, 0x8557a583,
|
||||
0x7faf0073, 0x5ab281b4, 0x34dbbac6, 0x8a0bc7cd,
|
||||
0x52584248, 0x3c3ef309, 0x41403737, 0x8200991d,
|
||||
0x7e0dfb86, 0xea1e3a8f, 0x5b87ca8a, 0x004be481,
|
||||
0x74e9fd6f, 0x80d518d6, 0xf10672c8, 0x2b8936b5,
|
||||
0xd7092242, 0xbaa950a4, 0xaa6a2305, 0xeccbb48b,
|
||||
0x43f6b561, 0x8607570a, 0x6143ba7b, 0x4c534447,
|
||||
0x45d97f76, 0x0ccf7b83, 0xd89482bd, 0x32c46a60,
|
||||
0x6db7b842, 0x0f7ad008, 0x4ce4968c, 0x2af52761,
|
||||
0x26a2a653, 0x5806f996, 0xfe844901, 0x6164e754,
|
||||
0xaf9287ab, 0x1f495a8d, 0x6cd70b5e, 0x681df673,
|
||||
0xc94dc88f, 0x4b9650f8, 0xdfc826d9, 0xb5710e59,
|
||||
0x80ed0f08, 0x615ce9c2, 0x0864130d, 0xc604520e,
|
||||
0x9be149db, 0xeefb463f, 0x15b7e000, 0xc3bf13ab,
|
||||
0x29d75556, 0x99420678, 0x505b5858, 0x6dadaeae,
|
||||
0xf87f8f56, 0xe9be5867, 0xd772475a, 0x0a4642c0,
|
||||
0xc59b2b86, 0x9e0f0a7f, 0x4c54834f, 0xb39f1d7c,
|
||||
0xd52dac56, 0x1fdde74b, 0x60fddc1c, 0x367321f1,
|
||||
0x98a7c9bd, 0x9a7896d2, 0x8d1f200b, 0x7975e907,
|
||||
0x0e7d4411, 0x1671c027, 0x438550a2, 0x385dfc21,
|
||||
0xb26c638d, 0x9b43b0d2, 0x03a0512d, 0x6b195c14,
|
||||
0x9db53322, 0x78512b73, 0x86714a5b, 0x9b900bb3,
|
||||
0xdbd702f9, 0xcdb985cb, 0x1033fd1e, 0xc75ed099,
|
||||
0x8a8c99fc, 0x12c5b949, 0x913249a0, 0xbd40f4b1,
|
||||
0x87406189, 0x977927e0, 0x76915a37, 0x79ffa5f2,
|
||||
0x5e1812b8, 0x8e7eb819, 0x6bfc46a5, 0x8d80c798,
|
||||
0x56d5a7ec, 0x5904350a, 0x82a1b59a, 0x27c64a52,
|
||||
0x4effaac0, 0x8e1519ec, 0x29ffed29, 0x3eaccc55,
|
||||
0x823e79c1, 0xdb5f2295, 0xb6ab9c23, 0xb301f2c5,
|
||||
0xe17f14f3, 0xf4e8892a, 0x107c9db8, 0x6a8a8ff4,
|
||||
0xaf9df422, 0xb14bd8f4, 0x00fa2a4c, 0x15324701,
|
||||
0x95e86a3b, 0xf74566e1, 0x386a788f, 0x9333e875,
|
||||
0xdea61190, 0x307a5338, 0xd9cec152, 0xe77165da,
|
||||
0x54187a14, 0x9a7d99bf, 0x4b31e986, 0x7d7ed557,
|
||||
0x626bb548, 0x434c4a78, 0x562b1588, 0xe0d15f63,
|
||||
0x524473f7, 0x484459e1, 0xbe617125, 0xb96f7eb8,
|
||||
0xb86620f7, 0xcc1e09b1, 0x7ad3b154, 0xae1f697e,
|
||||
0x11d0bfb1, 0xb1218568, 0x83a44b34, 0xeecec8bc,
|
||||
0xa06b01d8, 0xccadf143, 0xe1f9702c, 0x1e7c3d0d,
|
||||
0xd907d836, 0x780b3a02, 0x9a5e81fa, 0x0015cf61,
|
||||
0xbd148c0c, 0x84a65389, 0x99e77502, 0x0d630a94,
|
||||
0xd7f97779, 0x75567907, 0xa859be05, 0x8baab7b7,
|
||||
0x4f1a8101, 0x9992f951, 0xdd918c8a, 0x12b3ca17,
|
||||
0x117358b4, 0xf27a4783, 0xe3363be6, 0x3847f05d,
|
||||
0xb642595a, 0x4fbb98ae, 0xd6259c55, 0x3c72ff94,
|
||||
0xa9c3e102, 0x256e26c1, 0x2faf190b, 0xaaa1d198,
|
||||
0x8e25fc06, 0x8aa6fc5d, 0x9b994d46, 0x15045f23,
|
||||
0x23813558, 0x0173ef1b, 0xe4198a76, 0x36aa0de4,
|
||||
0x341d7595, 0xe186740f, 0xec371375, 0x1a4cabbe,
|
||||
0x6241897f, 0x388bd888, 0x2542e1f7, 0x61620df5,
|
||||
0x209f9d94, 0xca90f89b, 0x286a3e92, 0xea1cc30f,
|
||||
0x838ba96f, 0x4f0239d3, 0xf295395e, 0xb3c38631,
|
||||
0x7ea7a143, 0x157a4e43, 0x46f8173f, 0xfbc18d4a,
|
||||
0xc401e17a, 0xc4620358, 0xd2ab5437, 0xa01db06f,
|
||||
0x58ce91fc, 0x850de1a3, 0x9b542dba, 0xee77f038,
|
||||
0xddd3ced6, 0xc225d2ce, 0x63a3f765, 0x3342a06c,
|
||||
0x6a780c2f, 0xfaa925b2, 0x366ebeec, 0xbcc9abea,
|
||||
0xc7b3fa4e, 0xf4f1123d, 0x5198702c, 0x3e3458b7,
|
||||
0x0b1ce9a1, 0x51b1bd7f, 0x711e791e, 0x927d8bed,
|
||||
0x91dbaea9, 0x7eefbda9, 0x7a19edd9, 0xdf7b8dce,
|
||||
0x5bb40613, 0x0b0c1e0f, 0x85b82c98, 0x18da4dc1,
|
||||
0xc5fd78ac, 0x57c1e31d, 0x4c4001b5, 0xe31d2643,
|
||||
0xa6afbf58, 0xad200e68, 0xf0114ba4, 0xd6a620f2,
|
||||
0xc753a720, 0xac9022a0, 0x28a41f01, 0x22a4ba95,
|
||||
0xc00b7531, 0x23d42795, 0xcd836a86, 0x90262708,
|
||||
0x3292cad0, 0x40022e39, 0xc1581b0a, 0xe5101550,
|
||||
0x6538096b, 0x208c549d, 0x3ce2bf88, 0xa71df38e,
|
||||
0x3dec3685, 0xca3949f1, 0x79f3ad1b, 0x3ee8b300,
|
||||
0x9d305fc6, 0x7a2e5288, 0xbe81a2f2, 0x7ada0c06,
|
||||
0x191c7f01, 0x58dfcbd1, 0xc78dee72, 0x72364226,
|
||||
0x1866de12, 0x8d22305c, 0x943a0f0e, 0xc81967ff,
|
||||
0x4d55fb0f, 0xaf199be1, 0x90bbda61, 0x4e7c234f,
|
||||
0x90cfec16, 0x9b4bcf26, 0x21622023, 0x0926f0fa,
|
||||
0x1d504377, 0xa58db427, 0x8d93ce2b, 0x90bfe900,
|
||||
0x29e67397, 0x2c1261ed, 0x4ace9474, 0xd5c60282,
|
||||
0xe53fb300, 0x8a61a0ab, 0xa7aa0918, 0x4389d7c5,
|
||||
0xd09d605c, 0x6c5bedb5, 0xd6d54c51, 0x433dea21,
|
||||
0x7ad9e677, 0x813bff76, 0x5a162c75, 0x1ee0661f,
|
||||
0x9b6c2030, 0x8e8dc989, 0xcd4bc9fc, 0x4454675b,
|
||||
0x8d583c9c, 0xe3400094, 0x116ebb83, 0xe847bc9a,
|
||||
0x2a4622dd, 0x2a901e6f, 0xd789b1c0, 0x094e2bbb,
|
||||
0x056e563f, 0x9f17e606, 0x8bc79b8d, 0xd2c535c1,
|
||||
0x06a45a27, 0x9dc56771, 0xa06649e2, 0x5ff25ac8,
|
||||
0x6554961e, 0x98e583d9, 0x38ba93da, 0xdee1de18,
|
||||
0x037cb9d5, 0x6b17f195, 0x3431faaf, 0x13860a0d,
|
||||
0x28bca10d, 0x0a54c011, 0x9957cdb6, 0x3aa1f429,
|
||||
0x9d41b7b3, 0x9aea5be2, 0x60c7ce6b, 0x4cd1c10b,
|
||||
0x24ddddcd, 0xe28412ba, 0xa03a5466, 0xa1896879,
|
||||
0x59edcb87, 0x1b241765, 0x157bf161, 0xf219f950,
|
||||
0xe86ff526, 0x262005d9, 0x11769531, 0xbca15d95,
|
||||
0x28f5ef17, 0x1f27e725, 0xc32631d2, 0x07249e61,
|
||||
0x1ba851e3, 0x4f49b577, 0xe2a1df5e, 0x826fa7ff,
|
||||
0xc34e1e2e, 0x7fe26024, 0xbc19800f, 0x0d368dc9,
|
||||
0xe03da0c6, 0xadaa4f9c, 0x9ad1e43c, 0x96f84e44,
|
||||
0x0b6cd695, 0x1bb46971, 0x942d6e5b, 0x6316170d,
|
||||
0x3164509f, 0xc6659450, 0xb2a0370a, 0xabc208e8,
|
||||
0x6d479811, 0x3684bc0e, 0x80b7b101, 0xa50b7bb5,
|
||||
0x43d21233, 0xb423559d, 0xf41dcd16, 0xdfd3c276,
|
||||
0x3e586469, 0xd9b7630a, 0xb88f9e44, 0x0cda6f4d,
|
||||
0xe5bf5844, 0x8709f788, 0xdae37da6, 0x1fb41777,
|
||||
0x1d903f69, 0x34383b69, 0xd409ae70, 0xd1c99758,
|
||||
0xdedfd7a4, 0xa4bdf018, 0xf4058202, 0x8565d66f,
|
||||
0x5365aed9, 0xfa69742e, 0x2cfbfbcf, 0x88a00b60,
|
||||
0x506c0713, 0x2866475b, 0x3e1df573, 0xb86f7feb,
|
||||
0x31d23a7f, 0xc6320e6a, 0x3ebbc2a5, 0x83a1d4ef,
|
||||
0x15169f5f, 0x42a61753, 0x893e553e, 0x4ddbc66d,
|
||||
0x7449ec1f, 0x76f65d22, 0x0622e13b, 0x32986f89,
|
||||
0x21181b4b, 0x99a80c0a, 0xd6fe00b0, 0x282c0e81,
|
||||
0x9fc1cf88, 0x919b855d, 0x618257d8, 0x82c448b8,
|
||||
0xe22537a1, 0xa90de388, 0xba73b90c, 0xd765eeb0,
|
||||
0x62b2727e, 0xa08dfe20, 0x70b3c8c5, 0x3ef04007,
|
||||
0x9f73732b, 0x2201edd7, 0xb836219c, 0xf913af7c,
|
||||
0xf50f64ca, 0x93ac107a, 0xf509f84a, 0x6f6026f6,
|
||||
0xd9bb8eac, 0x4b268cfa, 0xa65a3fa6, 0x9837cb75,
|
||||
0x784fb835, 0x2060576d, 0xb1604cae, 0xb9da4116,
|
||||
0xab320cf2, 0x60a1b501, 0x0c73fa79, 0x8d5a6f1e,
|
||||
0x57688086, 0x218e4005, 0xca054e3d, 0xc1a3c3ec,
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/chip.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <cpu/intel/microcode.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
|
||||
static uint32_t microcode_updates[] = {
|
||||
/* WARNING - Intel has a new data structure that has variable length
|
||||
* microcode update lengths. They are encoded in int 8 and 9. A
|
||||
* dummy header of nulls must terminate the list.
|
||||
*/
|
||||
#include "microcode_MU16810d.h"
|
||||
#include "microcode_MU16930c.h"
|
||||
/* Dummy terminator */
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
};
|
||||
|
||||
|
||||
static void model_f0x_init(device_t dev)
|
||||
{
|
||||
/* Turn on caching if we haven't already */
|
||||
x86_enable_cache();
|
||||
x86_mtrr_check();
|
||||
|
||||
/* Update the microcode */
|
||||
intel_update_microcode(microcode_updates);
|
||||
|
||||
/* Enable the local cpu apics */
|
||||
setup_lapic();
|
||||
};
|
||||
|
||||
static struct device_operations cpu_dev_ops = {
|
||||
.init = model_f0x_init,
|
||||
};
|
||||
static struct cpu_device_id cpu_table[] = {
|
||||
{ X86_VENDOR_INTEL, 0x0672 },
|
||||
{ X86_VENDOR_INTEL, 0x0673 },
|
||||
{ X86_VENDOR_INTEL, 0x0681 },
|
||||
{ X86_VENDOR_INTEL, 0x0683 },
|
||||
{ X86_VENDOR_INTEL, 0x0686 },
|
||||
{ X86_VENDOR_INTEL, 0x06A0 },
|
||||
{ X86_VENDOR_INTEL, 0x06A1 },
|
||||
{ X86_VENDOR_INTEL, 0x06A4 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static struct cpu_driver driver __cpu_driver = {
|
||||
.ops = &cpu_dev_ops,
|
||||
.id_table = cpu_table,
|
||||
};
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
dir /cpu/x86/tsc
|
||||
dir /cpu/x86/mtrr
|
||||
dir /cpu/x86/fpu
|
||||
dir /cpu/x86/mmx
|
||||
dir /cpu/x86/sse
|
||||
dir /cpu/x86/lapic
|
||||
dir /cpu/x86/cache
|
||||
dir /cpu/intel/microcode
|
||||
driver model_f0x_init.o
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/chip.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <cpu/intel/microcode.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
|
||||
/* 256KB cache */
|
||||
static uint32_t microcode_updates[] = {
|
||||
/* WARNING - Intel has a new data structure that has variable length
|
||||
* microcode update lengths. They are encoded in int 8 and 9. A
|
||||
* dummy header of nulls must terminate the list.
|
||||
*/
|
||||
|
||||
/* Dummy terminator */
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
};
|
||||
|
||||
|
||||
static void model_f0x_init(device_t dev)
|
||||
{
|
||||
/* Turn on caching if we haven't already */
|
||||
x86_enable_cache();
|
||||
x86_setup_mtrrs();
|
||||
x86_mtrr_check();
|
||||
|
||||
/* Update the microcode */
|
||||
intel_update_microcode(microcode_updates);
|
||||
|
||||
/* Enable the local cpu apics */
|
||||
setup_lapic();
|
||||
};
|
||||
|
||||
static struct device_operations cpu_dev_ops = {
|
||||
.init = model_f0x_init,
|
||||
};
|
||||
static struct cpu_device_id cpu_table[] = {
|
||||
{ X86_VENDOR_INTEL, 0x0f0A },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static struct cpu_driver driver __cpu_driver = {
|
||||
.ops = &cpu_dev_ops,
|
||||
.id_table = cpu_table,
|
||||
};
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
|
||||
/*
|
||||
** NMI A20M IGNNE INTR
|
||||
* X8 H H H H
|
||||
* X9 H H H L projected
|
||||
* X10 H H L H
|
||||
* X11 H H L L
|
||||
* X12 H L H H
|
||||
* X13 H L H L
|
||||
* X14 H L L H
|
||||
* X15 H L L L
|
||||
* X16 L H H H
|
||||
* X17 L H H L
|
||||
* X18 L H L H
|
||||
* X19 L H L L
|
||||
* X20 L L H H
|
||||
* X21 L L H L projected
|
||||
* X22 L L L H projected
|
||||
* X23 L L L L projected
|
||||
*
|
||||
** NMI INTR IGNNE A20M
|
||||
* X8 H H H H
|
||||
* X9 H L H H projected
|
||||
* X10 H H L H
|
||||
* X11 H L L H
|
||||
* X12 H H H L
|
||||
* X13 H L H L
|
||||
* X14 H H L L
|
||||
* X15 H L L L
|
||||
* X16 L H H H
|
||||
* X17 L L H H
|
||||
* X18 L H L H
|
||||
* X19 L L L H
|
||||
* X20 L H H L
|
||||
* X21 L L H L projected
|
||||
* X22 L H L L projected
|
||||
* X23 L L L L projected
|
||||
*/
|
||||
|
||||
#define XEON_X8 0xf
|
||||
#define XEON_X9 0xb /* projected */
|
||||
#define XEON_X10 0xd
|
||||
#define XEON_X11 0x9
|
||||
#define XEON_X12 0xe
|
||||
#define XEON_X13 0xa
|
||||
#define XEON_X14 0xc
|
||||
#define XEON_X15 0x8
|
||||
#define XEON_X16 0x7
|
||||
#define XEON_X17 0x3
|
||||
#define XEON_X18 0x5
|
||||
#define XEON_X19 0x1
|
||||
#define XEON_X20 0x6
|
||||
#define XEON_X21 0x2 /* projected */
|
||||
#define XEON_X22 0x4 /* projected */
|
||||
#define XEON_X23 0x0 /* projected */
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
dir /cpu/x86/tsc
|
||||
dir /cpu/x86/mtrr
|
||||
dir /cpu/x86/fpu
|
||||
dir /cpu/x86/mmx
|
||||
dir /cpu/x86/sse
|
||||
dir /cpu/x86/lapic
|
||||
dir /cpu/x86/cache
|
||||
dir /cpu/intel/microcode
|
||||
driver model_f1x_init.o
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/chip.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <cpu/intel/microcode.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
|
||||
/* 256KB cache */
|
||||
static uint32_t microcode_updates[] = {
|
||||
/* WARNING - Intel has a new data structure that has variable length
|
||||
* microcode update lengths. They are encoded in int 8 and 9. A
|
||||
* dummy header of nulls must terminate the list.
|
||||
*/
|
||||
|
||||
/* Dummy terminator */
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
};
|
||||
|
||||
|
||||
static void model_f1x_init(device_t dev)
|
||||
{
|
||||
/* Turn on caching if we haven't already */
|
||||
x86_enable_cache();
|
||||
x86_setup_mtrrs();
|
||||
x86_mtrr_check();
|
||||
|
||||
/* Update the microcode */
|
||||
intel_update_microcode(microcode_updates);
|
||||
|
||||
/* Enable the local cpu apics */
|
||||
setup_lapic();
|
||||
};
|
||||
|
||||
static struct device_operations cpu_dev_ops = {
|
||||
.init = model_f1x_init,
|
||||
};
|
||||
static struct cpu_device_id cpu_table[] = {
|
||||
{ X86_VENDOR_INTEL, 0x0f12 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static struct cpu_driver driver __cpu_driver = {
|
||||
.ops = &cpu_dev_ops,
|
||||
.id_table = cpu_table,
|
||||
};
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
|
||||
/*
|
||||
** NMI A20M IGNNE INTR
|
||||
* X8 H H H H
|
||||
* X9 H H H L projected
|
||||
* X10 H H L H
|
||||
* X11 H H L L
|
||||
* X12 H L H H
|
||||
* X13 H L H L
|
||||
* X14 H L L H
|
||||
* X15 H L L L
|
||||
* X16 L H H H
|
||||
* X17 L H H L
|
||||
* X18 L H L H
|
||||
* X19 L H L L
|
||||
* X20 L L H H
|
||||
* X21 L L H L projected
|
||||
* X22 L L L H projected
|
||||
* X23 L L L L projected
|
||||
*
|
||||
** NMI INTR IGNNE A20M
|
||||
* X8 H H H H
|
||||
* X9 H L H H projected
|
||||
* X10 H H L H
|
||||
* X11 H L L H
|
||||
* X12 H H H L
|
||||
* X13 H L H L
|
||||
* X14 H H L L
|
||||
* X15 H L L L
|
||||
* X16 L H H H
|
||||
* X17 L L H H
|
||||
* X18 L H L H
|
||||
* X19 L L L H
|
||||
* X20 L H H L
|
||||
* X21 L L H L projected
|
||||
* X22 L H L L projected
|
||||
* X23 L L L L projected
|
||||
*/
|
||||
|
||||
#define XEON_X8 0xf
|
||||
#define XEON_X9 0xb /* projected */
|
||||
#define XEON_X10 0xd
|
||||
#define XEON_X11 0x9
|
||||
#define XEON_X12 0xe
|
||||
#define XEON_X13 0xa
|
||||
#define XEON_X14 0xc
|
||||
#define XEON_X15 0x8
|
||||
#define XEON_X16 0x7
|
||||
#define XEON_X17 0x3
|
||||
#define XEON_X18 0x5
|
||||
#define XEON_X19 0x1
|
||||
#define XEON_X20 0x6
|
||||
#define XEON_X21 0x2 /* projected */
|
||||
#define XEON_X22 0x4 /* projected */
|
||||
#define XEON_X23 0x0 /* projected */
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
dir /cpu/x86/tsc
|
||||
dir /cpu/x86/mtrr
|
||||
dir /cpu/x86/fpu
|
||||
dir /cpu/x86/mmx
|
||||
dir /cpu/x86/sse
|
||||
dir /cpu/x86/lapic
|
||||
dir /cpu/x86/cache
|
||||
dir /cpu/intel/microcode
|
||||
dir /cpu/intel/hyperthreading
|
||||
driver model_f1x_init.o
|
||||
|
|
@ -0,0 +1,513 @@
|
|||
/* from file m02f2203.txt */
|
||||
0x000000001, // Header Version
|
||||
0x000000003, // Patch ID
|
||||
0x004062002, // DATE
|
||||
0x000000f22, // CPUID
|
||||
0x0664ee8e8, // Checksum
|
||||
0x000000001, // Loader Version
|
||||
0x000000002, // Platform ID
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x0377de33f,
|
||||
0x01d618b92,
|
||||
0x0e61cc8ec,
|
||||
0x025bdbc5c,
|
||||
0x0ebb0b548,
|
||||
0x06ee11a02,
|
||||
0x0d14e18de,
|
||||
0x0f5e03a4f,
|
||||
0x04981631f,
|
||||
0x0b0df6b8b,
|
||||
0x03c8008c2,
|
||||
0x0f5a0a36b,
|
||||
0x08cd685ec,
|
||||
0x0e145d134,
|
||||
0x037a27f9f,
|
||||
0x022dcc294,
|
||||
0x0601d7784,
|
||||
0x03d5e32a8,
|
||||
0x0a492144c,
|
||||
0x06657dae6,
|
||||
0x0a4ce4415,
|
||||
0x074e3598c,
|
||||
0x01789ba2b,
|
||||
0x0e3834a55,
|
||||
0x0c2231988,
|
||||
0x0aa27a4ae,
|
||||
0x0114d2424,
|
||||
0x07589cecd,
|
||||
0x0caadbccf,
|
||||
0x0e0303485,
|
||||
0x0120df375,
|
||||
0x01e6bc5a7,
|
||||
0x028b214f7,
|
||||
0x02afafb93,
|
||||
0x069f91ee7,
|
||||
0x0aa458dd2,
|
||||
0x01725310e,
|
||||
0x08e031806,
|
||||
0x06fc04854,
|
||||
0x004d60f22,
|
||||
0x0c3f9a443,
|
||||
0x06a08d56a,
|
||||
0x0ccf7ad29,
|
||||
0x082c4a0da,
|
||||
0x0a42aa3a5,
|
||||
0x0b6bf9b3c,
|
||||
0x0d3a51840,
|
||||
0x0f9199ece,
|
||||
0x04efeca48,
|
||||
0x0a6bfccea,
|
||||
0x0a8059c00,
|
||||
0x0cf20feb3,
|
||||
0x09fa06479,
|
||||
0x0ba0445a1,
|
||||
0x0d99299fe,
|
||||
0x018070156,
|
||||
0x0343b5abc,
|
||||
0x0dbfc936f,
|
||||
0x0b7d1da3c,
|
||||
0x0c1e0163e,
|
||||
0x0d6959470,
|
||||
0x0226de13d,
|
||||
0x02e139add,
|
||||
0x05f43064b,
|
||||
0x0ce983b01,
|
||||
0x0bc342c48,
|
||||
0x0d9ec8404,
|
||||
0x09f1f147a,
|
||||
0x0c522f601,
|
||||
0x0941685c6,
|
||||
0x07a4e3e91,
|
||||
0x06f634c7e,
|
||||
0x0024bf95c,
|
||||
0x0b0d57cc0,
|
||||
0x0431f0d06,
|
||||
0x015609941,
|
||||
0x0b1f48eb8,
|
||||
0x01fd617e1,
|
||||
0x055a096fb,
|
||||
0x0e0295335,
|
||||
0x058f91fce,
|
||||
0x0a36f4c53,
|
||||
0x065590ba8,
|
||||
0x0d6a57716,
|
||||
0x0cf117678,
|
||||
0x0438bd8a6,
|
||||
0x0ac42c261,
|
||||
0x098d06a30,
|
||||
0x00d38a2c0,
|
||||
0x057a732a7,
|
||||
0x0ca0d4460,
|
||||
0x0a4e557cc,
|
||||
0x03e6f9c5d,
|
||||
0x0fdef3103,
|
||||
0x0ed9104f4,
|
||||
0x02a2ced76,
|
||||
0x0869c87f6,
|
||||
0x01e710fdf,
|
||||
0x04ef40d17,
|
||||
0x054bf6b84,
|
||||
0x046606228,
|
||||
0x010615915,
|
||||
0x05735682e,
|
||||
0x03480da05,
|
||||
0x0c07bc8ac,
|
||||
0x01012738e,
|
||||
0x0e3465cf3,
|
||||
0x081341a97,
|
||||
0x0934e1282,
|
||||
0x075ec3f41,
|
||||
0x0c5ea60c5,
|
||||
0x05c0afb0c,
|
||||
0x07731f128,
|
||||
0x02bc1c468,
|
||||
0x07ef85ad1,
|
||||
0x07a4f9311,
|
||||
0x00fe965b0,
|
||||
0x040bc930f,
|
||||
0x023e38027,
|
||||
0x0f9624477,
|
||||
0x0b65c0735,
|
||||
0x030e0d716,
|
||||
0x0e2c53914,
|
||||
0x0ba8abecc,
|
||||
0x0619d1103,
|
||||
0x0bd77536b,
|
||||
0x09ae818fa,
|
||||
0x0bc595a04,
|
||||
0x064cc8c46,
|
||||
0x0a555a73b,
|
||||
0x052e27c72,
|
||||
0x0c241a051,
|
||||
0x0bda999c7,
|
||||
0x054fbcbad,
|
||||
0x06781bb03,
|
||||
0x08bbf9806,
|
||||
0x07bd81ab5,
|
||||
0x0978054d9,
|
||||
0x00d2d4198,
|
||||
0x08be28922,
|
||||
0x0d4b1067e,
|
||||
0x09dbb52bd,
|
||||
0x03ddf0f34,
|
||||
0x075cca964,
|
||||
0x037dc6270,
|
||||
0x09dc8a692,
|
||||
0x080fc4514,
|
||||
0x054c9a832,
|
||||
0x084ddbc69,
|
||||
0x00ac3d725,
|
||||
0x009d8381e,
|
||||
0x0891aac6f,
|
||||
0x0dcd35e28,
|
||||
0x09ed405a3,
|
||||
0x0c099862e,
|
||||
0x0701e616f,
|
||||
0x0d1e4f9f7,
|
||||
0x0252690fc,
|
||||
0x0109f0ec8,
|
||||
0x0c2894c0b,
|
||||
0x0f528565d,
|
||||
0x0ec8dd34a,
|
||||
0x0961e7f8a,
|
||||
0x0a9ce0635,
|
||||
0x09bcffe26,
|
||||
0x067e08a77,
|
||||
0x00d1e13b5,
|
||||
0x0f102b8f9,
|
||||
0x0c46f8884,
|
||||
0x0e876ee7f,
|
||||
0x094a8de36,
|
||||
0x0449d3555,
|
||||
0x0cf6dfbbc,
|
||||
0x08740a116,
|
||||
0x0e9e838fe,
|
||||
0x0c8870163,
|
||||
0x012dd5605,
|
||||
0x0ab15f930,
|
||||
0x00b38c94c,
|
||||
0x0f2a70faf,
|
||||
0x0acd8acb3,
|
||||
0x0e5f84145,
|
||||
0x0b3721d0a,
|
||||
0x007c8afce,
|
||||
0x000fd2e3a,
|
||||
0x0c54c4695,
|
||||
0x02194cdbf,
|
||||
0x0fd5feb3f,
|
||||
0x05dedb9eb,
|
||||
0x0ad01df81,
|
||||
0x06bba699b,
|
||||
0x01cd736aa,
|
||||
0x005b4b6e7,
|
||||
0x0f170db07,
|
||||
0x0823a9983,
|
||||
0x04886461f,
|
||||
0x07a7f266b,
|
||||
0x0232b1209,
|
||||
0x08e48c22b,
|
||||
0x0dd54eda3,
|
||||
0x074eb5922,
|
||||
0x0bffddb2a,
|
||||
0x0d6d3a551,
|
||||
0x0a00c66ea,
|
||||
0x0feaa9c65,
|
||||
0x069b3f0f1,
|
||||
0x0467dcf38,
|
||||
0x0be819529,
|
||||
0x04ec7cd2f,
|
||||
0x0b77e3247,
|
||||
0x0ceaa22b5,
|
||||
0x08e51809b,
|
||||
0x0265fd218,
|
||||
0x0c70e0091,
|
||||
0x09642d9ef,
|
||||
0x0ee020d62,
|
||||
0x0770832d0,
|
||||
0x05085caf9,
|
||||
0x062f5c49e,
|
||||
0x0081af519,
|
||||
0x065607fde,
|
||||
0x0097386eb,
|
||||
0x0718f2e33,
|
||||
0x05f2f72ac,
|
||||
0x0460b4d33,
|
||||
0x084f73cbd,
|
||||
0x0de490896,
|
||||
0x0960e980a,
|
||||
0x051939fbc,
|
||||
0x0edb15e28,
|
||||
0x017c027ec,
|
||||
0x09012a039,
|
||||
0x0db29ee45,
|
||||
0x04b29253f,
|
||||
0x04802bbaf,
|
||||
0x006b1acfc,
|
||||
0x0972749b5,
|
||||
0x05b4906f7,
|
||||
0x0247eb936,
|
||||
0x0bbcd86c5,
|
||||
0x0d076e120,
|
||||
0x042a724d6,
|
||||
0x09fcb4abc,
|
||||
0x00dbb0214,
|
||||
0x006fc5700,
|
||||
0x00066d96c,
|
||||
0x0e7f787bf,
|
||||
0x0f40260c8,
|
||||
0x0f6b9aec7,
|
||||
0x063bc2fc7,
|
||||
0x054731138,
|
||||
0x0855aff40,
|
||||
0x08e90936c,
|
||||
0x01c248914,
|
||||
0x085e9a734,
|
||||
0x0b95428ac,
|
||||
0x07ace1ea4,
|
||||
0x0d2a00b9b,
|
||||
0x0c8d010ae,
|
||||
0x0bc486961,
|
||||
0x0bc247ea5,
|
||||
0x0e5ecce2c,
|
||||
0x0b04d8d96,
|
||||
0x056492f0e,
|
||||
0x017d42ee8,
|
||||
0x088e4f602,
|
||||
0x018309b49,
|
||||
0x00fbeaae6,
|
||||
0x02104532c,
|
||||
0x0fcd354b7,
|
||||
0x0bf05a589,
|
||||
0x0848d50d0,
|
||||
0x060c00a26,
|
||||
0x0ed5b1a58,
|
||||
0x08e6f15e5,
|
||||
0x0a2fd3ba9,
|
||||
0x0bd11eb0f,
|
||||
0x0a13c8c73,
|
||||
0x03e314454,
|
||||
0x0a55a2e36,
|
||||
0x05624ec02,
|
||||
0x07cdadfcb,
|
||||
0x0c404b866,
|
||||
0x0cf27534f,
|
||||
0x0ade78324,
|
||||
0x0153bc559,
|
||||
0x0388f0fe2,
|
||||
0x0d84a69f5,
|
||||
0x03f3ea295,
|
||||
0x0a425162a,
|
||||
0x02b00dfb7,
|
||||
0x0ad9c000f,
|
||||
0x027dc1459,
|
||||
0x08a2a224b,
|
||||
0x0b3628846,
|
||||
0x0e68a8168,
|
||||
0x085800f6d,
|
||||
0x04bc08c07,
|
||||
0x05930d67c,
|
||||
0x064f9bb38,
|
||||
0x09e1a5f6a,
|
||||
0x05b59e3af,
|
||||
0x0b65baf5b,
|
||||
0x00c33aab0,
|
||||
0x0da3458c6,
|
||||
0x0ab574a23,
|
||||
0x0b5f15e34,
|
||||
0x0e9caf076,
|
||||
0x0c9f740c3,
|
||||
0x0c6adc9f5,
|
||||
0x0f046920f,
|
||||
0x0a49b2ca7,
|
||||
0x0083b3f30,
|
||||
0x0d17f0742,
|
||||
0x00abea9b1,
|
||||
0x0d7a83756,
|
||||
0x0276d235b,
|
||||
0x07b2461d5,
|
||||
0x0e78d4341,
|
||||
0x0474a3a2b,
|
||||
0x0620402f1,
|
||||
0x0ad29ce1b,
|
||||
0x0a73bc19f,
|
||||
0x0c20ecdc6,
|
||||
0x0bf8bdae0,
|
||||
0x0457c7d70,
|
||||
0x083dc0fc0,
|
||||
0x0707b6a23,
|
||||
0x0bb2fc9c5,
|
||||
0x02ea50b16,
|
||||
0x0b3dba5ee,
|
||||
0x0b8ca98e7,
|
||||
0x0555e3750,
|
||||
0x0caa69ccd,
|
||||
0x040f84ca1,
|
||||
0x0f8fa5205,
|
||||
0x04aaea9d1,
|
||||
0x0410bc48b,
|
||||
0x094f8e471,
|
||||
0x085fdf713,
|
||||
0x0025fe222,
|
||||
0x038a1044f,
|
||||
0x0dacdbbef,
|
||||
0x0b5015882,
|
||||
0x056ab6bb5,
|
||||
0x0b2152d43,
|
||||
0x0fdf7db82,
|
||||
0x02e36515e,
|
||||
0x0ad01b0e5,
|
||||
0x067d3f0b2,
|
||||
0x015a14ce8,
|
||||
0x029abb6f6,
|
||||
0x0a0c632b9,
|
||||
0x03c6ce83e,
|
||||
0x06446e87c,
|
||||
0x014505c45,
|
||||
0x046ce3802,
|
||||
0x088d6fb38,
|
||||
0x020f7fc23,
|
||||
0x06a83fe4a,
|
||||
0x01f7f37f7,
|
||||
0x090a9a5fb,
|
||||
0x040e0adf0,
|
||||
0x0814e5c1e,
|
||||
0x078cc452c,
|
||||
0x037648002,
|
||||
0x05988959e,
|
||||
0x0bbaa19fd,
|
||||
0x0c121b46f,
|
||||
0x0ce92151e,
|
||||
0x0edf5b014,
|
||||
0x0fe0d20b0,
|
||||
0x04893118b,
|
||||
0x00378e532,
|
||||
0x0548a7cda,
|
||||
0x00b7d8b2c,
|
||||
0x0efc71f0f,
|
||||
0x06132e9ab,
|
||||
0x0cef71af6,
|
||||
0x065bc1c9e,
|
||||
0x0c6aaf262,
|
||||
0x0af387a4f,
|
||||
0x00cf65fd4,
|
||||
0x0c04ec9cf,
|
||||
0x0d2c2efb1,
|
||||
0x0192f4d47,
|
||||
0x06ac59280,
|
||||
0x0d49ab94e,
|
||||
0x0052d901c,
|
||||
0x07c2f1090,
|
||||
0x0b21ead2e,
|
||||
0x042710177,
|
||||
0x05967e722,
|
||||
0x0dedd9459,
|
||||
0x0e270eff1,
|
||||
0x04bf447cd,
|
||||
0x0027dd494,
|
||||
0x045d7ddaa,
|
||||
0x074400df4,
|
||||
0x01912fd71,
|
||||
0x0947c18ec,
|
||||
0x0faf5298d,
|
||||
0x01de16144,
|
||||
0x0627c2e4a,
|
||||
0x0fae7b523,
|
||||
0x06edc73b2,
|
||||
0x0af4fdf41,
|
||||
0x06c3ab948,
|
||||
0x083e9d603,
|
||||
0x0a57f809c,
|
||||
0x0404f32a3,
|
||||
0x018206e38,
|
||||
0x0daf619d4,
|
||||
0x04fe5e6ab,
|
||||
0x0c1b989dc,
|
||||
0x0576e7bb1,
|
||||
0x094290c71,
|
||||
0x071e9a429,
|
||||
0x00e3b7a76,
|
||||
0x0f87f203a,
|
||||
0x0c8328af9,
|
||||
0x0225c8b85,
|
||||
0x0ae9152e4,
|
||||
0x0be5098a9,
|
||||
0x0022c34bc,
|
||||
0x0a2428231,
|
||||
0x01516ddab,
|
||||
0x048521134,
|
||||
0x04f0831ea,
|
||||
0x0f0cf7c5f,
|
||||
0x0be4c22bd,
|
||||
0x0a26fe115,
|
||||
0x0cf27284a,
|
||||
0x0cf0452e6,
|
||||
0x071ae625c,
|
||||
0x0208f6eb3,
|
||||
0x0aef04760,
|
||||
0x063ae718b,
|
||||
0x026609177,
|
||||
0x0c920ab17,
|
||||
0x006a839de,
|
||||
0x0a51b4ed2,
|
||||
0x075e98487,
|
||||
0x04344aa11,
|
||||
0x0405a801e,
|
||||
0x027b38539,
|
||||
0x0357cd7b9,
|
||||
0x042c92121,
|
||||
0x0df67217c,
|
||||
0x08be79011,
|
||||
0x0cb3c12d6,
|
||||
0x05f67e891,
|
||||
0x062716f33,
|
||||
0x06b816be3,
|
||||
0x076dd3151,
|
||||
0x077a9f91e,
|
||||
0x0568feafa,
|
||||
0x0e8f975bf,
|
||||
0x0da317523,
|
||||
0x071259d6d,
|
||||
0x08fa429cb,
|
||||
0x0a15c62f1,
|
||||
0x0699b4747,
|
||||
0x09aac9b7e,
|
||||
0x05fcc2aff,
|
||||
0x07345e53c,
|
||||
0x0a1017201,
|
||||
0x02312089e,
|
||||
0x0bf6321de,
|
||||
0x029253d28,
|
||||
0x0846a0aa5,
|
||||
0x0e4c32754,
|
||||
0x0b2757cc1,
|
||||
0x019684827,
|
||||
0x082b4de7d,
|
||||
0x0651855d0,
|
||||
0x04dc73308,
|
||||
0x0ba6e7198,
|
||||
0x07e5f0058,
|
||||
0x01979bd22,
|
||||
0x0f101b11c,
|
||||
0x078cf5a53,
|
||||
0x0421158de,
|
||||
0x0ec657dd4,
|
||||
0x09d27f154,
|
||||
0x0dcd23639,
|
||||
0x09f574023,
|
||||
0x0d0b67fc9,
|
||||
0x08e62bb83,
|
||||
0x0c7e731de,
|
||||
0x01af9743f,
|
||||
0x0b8a9b5de,
|
||||
0x0bc7cce1e,
|
||||
0x042959190,
|
||||
0x0a0c932e5,
|
||||
0x0baa1e41e,
|
||||
0x04902b20c,
|
||||
0x05aadd04b,
|
||||
0x0135baf90,
|
||||
0x0ac599606,
|
||||
|
|
@ -0,0 +1,140 @@
|
|||
|
||||
/* Intel xeon sig f24 pf 2 from m02f2410.txt */
|
||||
0x000000001, /* Header Version */
|
||||
0x000000010, /* Patch ID */
|
||||
0x007192002, /* DATE */
|
||||
0x000000f24, /* CPUID */
|
||||
0x0789bb8d7, /* Checksum */
|
||||
0x000000001, /* Loader Version */
|
||||
0x000000002, /* Platform ID */
|
||||
0x000000000, /* reserved */
|
||||
0x000000000, /* reserved */
|
||||
0x000000000, /* reserved */
|
||||
0x000000000, /* reserved */
|
||||
0x000000000, /* reserved */
|
||||
0x0ffffffe9, 0x05715f121, 0x0440ce2fa, 0x0d5d090eb,
|
||||
0x070b3e977, 0x092320e8c, 0x04f989906, 0x036907442,
|
||||
0x0cc4b12e2, 0x0b456a6ae, 0x00ad5bcf7, 0x0e9f0a425,
|
||||
0x070b932d2, 0x0e66202c9, 0x0350f8d4b, 0x0d560a828,
|
||||
0x0763e8420, 0x04595b38a, 0x0a66d6637, 0x0e2adc7be,
|
||||
0x0c5d9515e, 0x07d6d08cd, 0x0c930e826, 0x0528d413f,
|
||||
0x0ce5ac17a, 0x086b9646b, 0x0e7845b29, 0x00c56e922,
|
||||
0x0ad8a85f2, 0x08e9d478d, 0x0d6faa7f5, 0x0da7ac699,
|
||||
0x010859ceb, 0x00c7c1cd8, 0x0fd7bc59d, 0x0b847dddd,
|
||||
0x0e545057b, 0x05af340d6, 0x01e2f8c45, 0x026c9c8c6,
|
||||
0x08b6ea51c, 0x075280c65, 0x0eb953366, 0x06400e75d,
|
||||
0x0fe0be614, 0x04b47f2ca, 0x0ac119100, 0x02f973c6e,
|
||||
0x0e3600377, 0x0e234bd6c, 0x06010f6fb, 0x0497c113b,
|
||||
0x010824bec, 0x0e897a508, 0x00de50694, 0x08202b8a6,
|
||||
0x07d2c657d, 0x0a82cd03c, 0x060947d1b, 0x0de88dfb8,
|
||||
0x0be799b59, 0x0cfdfd29e, 0x03d9ac639, 0x0fb674628,
|
||||
0x041988eba, 0x0700ebe34, 0x0019565b3, 0x0d3be034d,
|
||||
0x04366d795, 0x087f1131c, 0x01f2d001d, 0x063db664a,
|
||||
0x09a846727, 0x00b4b7370, 0x044941cd5, 0x0f5974d99,
|
||||
0x0fcd2d1a4, 0x0f4a458ea, 0x04edc79ff, 0x02eb36b1d,
|
||||
0x02b1bf369, 0x0fbe64d3d, 0x0c15f0935, 0x0c6ba263b,
|
||||
0x064320f87, 0x0ab342765, 0x054316d17, 0x09ee930d7,
|
||||
0x024a1a577, 0x0340dad94, 0x03c48afa2, 0x090373ff8,
|
||||
0x097f5be99, 0x0ba7bca44, 0x0ca4dae6c, 0x06e46a894,
|
||||
0x060f0f843, 0x07cdc8649, 0x03314dbd3, 0x0948e0f5c,
|
||||
0x0e29fe95c, 0x0afe80cef, 0x0864ea1b7, 0x075578a0f,
|
||||
0x00a908830, 0x0d354ef34, 0x0e57a2d1f, 0x09568c18b,
|
||||
0x0da0d7051, 0x0c32910d9, 0x03592ce94, 0x0e5b78410,
|
||||
0x0a08bf5b4, 0x068862085, 0x0f0147e1e, 0x0e676dfdd,
|
||||
0x0083b0d3f, 0x0a8594085, 0x00427d952, 0x008433d45,
|
||||
0x064bc994d, 0x04aef1348, 0x056121cb5, 0x0dea1295b,
|
||||
0x082edfc21, 0x0dee5f488, 0x0d7aa494b, 0x01b1a908c,
|
||||
0x00aa4ec23, 0x0b00cb03d, 0x07935f381, 0x0d7d03c6d,
|
||||
0x0f1acd28d, 0x0c3552afc, 0x06019f316, 0x0a2e40e1d,
|
||||
0x02c0e8a2d, 0x07d5097ae, 0x0e4e79555, 0x0fb3b4469,
|
||||
0x0d03ad54a, 0x0c1f2dab9, 0x036d22f7d, 0x015720655,
|
||||
0x00eb840e2, 0x063fc319a, 0x0fc99b4fc, 0x096aba0a6,
|
||||
0x0c264ca2d, 0x0937b3bf1, 0x03f15de0f, 0x0389dc588,
|
||||
0x01f58b599, 0x094de6fa9, 0x09cfb142f, 0x0cba182e0,
|
||||
0x0adde1620, 0x0e12e4fbe, 0x07a0fa14f, 0x0f464c742,
|
||||
0x0d65b2240, 0x0537e32c2, 0x0fae621a1, 0x0c814bdfd,
|
||||
0x027cd2a15, 0x0ca48efbf, 0x0f2befd43, 0x0125f5190,
|
||||
0x04fd50b0f, 0x051fe985e, 0x03acab851, 0x0f3f43b0f,
|
||||
0x06752ff24, 0x0cb6e48c3, 0x00c7b4e8f, 0x04cde4d0d,
|
||||
0x063f612e2, 0x0ae429cb5, 0x048175667, 0x0ad4c222b,
|
||||
0x065cfbc13, 0x0dc5c7f7a, 0x01c4ca18c, 0x09dd9940f,
|
||||
0x05df52ad4, 0x026dc7a9d, 0x040c2ef10, 0x0eee8cccd,
|
||||
0x0733f9d40, 0x0b0b2d287, 0x02c63d214, 0x0280a8a8c,
|
||||
0x07d79140b, 0x02bbad4bc, 0x013d77277, 0x0b3b27d18,
|
||||
0x051c9fc03, 0x0cceb6183, 0x0b3d40b0a, 0x06db2dea2,
|
||||
0x0e20c32de, 0x09f1a1bef, 0x049904f2a, 0x0c785676a,
|
||||
0x05193462d, 0x0db728f55, 0x06e011412, 0x0a29fde6f,
|
||||
0x02db8336e, 0x030cd1f0b, 0x0facf0b4e, 0x0f7594816,
|
||||
0x0ae3aaa8f, 0x0bd281afd, 0x03bee7d6a, 0x00f4aa235,
|
||||
0x00239def7, 0x00a27a699, 0x0f4593d2a, 0x0ccba9e40,
|
||||
0x044139d91, 0x0c92b308d, 0x033a788e1, 0x065cdf1cb,
|
||||
0x03193eac8, 0x0f4d29608, 0x048df9a08, 0x084f4666b,
|
||||
0x032dd3402, 0x08577079a, 0x07d86e147, 0x0a3ebdcf8,
|
||||
0x01671b672, 0x0617cf22c, 0x0cabc0826, 0x0d97544af,
|
||||
0x0de1246a0, 0x0a0f7a0e2, 0x0ba17cc9a, 0x0225d62c9,
|
||||
0x034777700, 0x07d2b36f8, 0x0144da38f, 0x0cab82ce4,
|
||||
0x00ec7f553, 0x0b9500f28, 0x0601b48d4, 0x06c23042d,
|
||||
0x096d63b58, 0x0e0465458, 0x04210e46c, 0x0fa8a12c5,
|
||||
0x0260b6716, 0x09eaacd55, 0x01ae1fb31, 0x0d8b61299,
|
||||
0x03608653c, 0x07af8888b, 0x064962804, 0x0e88d60cc,
|
||||
0x083784b2a, 0x0df50de8d, 0x072d79fec, 0x04cf109f8,
|
||||
0x0d19f7b44, 0x0323ce9f5, 0x0bc30d1f0, 0x0fdf68aa7,
|
||||
0x0105c51c7, 0x0c82d9c10, 0x070caaa5d, 0x04f9e40b5,
|
||||
0x00df8d32c, 0x0e8ac017d, 0x0c0ce9e3a, 0x0e3e614fa,
|
||||
0x03d09d4ac, 0x0d728b0de, 0x0bfbb6ac2, 0x098944bc0,
|
||||
0x09966a062, 0x07825e582, 0x0a48ae982, 0x0c63e9f3f,
|
||||
0x01e964e46, 0x08fa03130, 0x065bab214, 0x059ed2c27,
|
||||
0x0e171d297, 0x06bbcf48f, 0x0ec6d44a8, 0x0ef452345,
|
||||
0x03beeeccf, 0x0e6b61e6c, 0x039ff1edd, 0x031ab1a3c,
|
||||
0x03c4823bd, 0x0f046d111, 0x0dc77d7ab, 0x089e45e10,
|
||||
0x0acb472d8, 0x0bf7f62f2, 0x0e0f89ec4, 0x0b8722c2c,
|
||||
0x05277f745, 0x0090cc66f, 0x0c7615dbb, 0x0f019f628,
|
||||
0x06d9d1d6f, 0x0a3a11844, 0x06f4ed58c, 0x070ea5292,
|
||||
0x0b629584b, 0x081914eb0, 0x0619d1ef6, 0x08124cf57,
|
||||
0x0ea8fc589, 0x02cb0f8aa, 0x07be467a0, 0x0b61a2958,
|
||||
0x0d5586daa, 0x0abe9f60d, 0x0693ebd44, 0x02129bc82,
|
||||
0x04dc303e6, 0x079b717ef, 0x0ce04087f, 0x0f2bedb88,
|
||||
0x053c57df0, 0x0c62d43cb, 0x0a2721d91, 0x04d1315ad,
|
||||
0x06e398fb8, 0x09cd1c3c6, 0x04e887872, 0x08f3caf22,
|
||||
0x0a514e19a, 0x0ddd376ad, 0x09cf2fe8c, 0x0adde0e06,
|
||||
0x049fd5014, 0x00eac54c5, 0x054dbe117, 0x0cc227f52,
|
||||
0x0f1764002, 0x0f6bedffd, 0x06da0a736, 0x010cbac3b,
|
||||
0x0cf5ad71f, 0x03e647786, 0x09b675662, 0x0bfc85a6e,
|
||||
0x08c125ae4, 0x08ad8df36, 0x0f1f6eef0, 0x06e8e868c,
|
||||
0x09657d971, 0x0cd72893d, 0x0940b4748, 0x0d7020293,
|
||||
0x04e0a55b1, 0x0c65a6b72, 0x06231f2c5, 0x0f7fac755,
|
||||
0x02d36efd8, 0x019cf2803, 0x02066d5f8, 0x0914eda50,
|
||||
0x06121bdbd, 0x09bbd2fb6, 0x097b7a60e, 0x01241a2cc,
|
||||
0x09aaa0715, 0x06a44b718, 0x05ebb4d17, 0x0f1dc871f,
|
||||
0x04986b486, 0x0892bf0dc, 0x0e6b6062a, 0x0228745a9,
|
||||
0x05035cfe0, 0x0d4fa406b, 0x033a99806, 0x080a510f2,
|
||||
0x053310cbe, 0x0d4fb73af, 0x0200e09ce, 0x0c7b5f89a,
|
||||
0x06c5c857a, 0x0f736be54, 0x0d642ff8f, 0x0ec3f5f37,
|
||||
0x0748990cf, 0x0e5057b8a, 0x0911e4cd8, 0x00e8af6f3,
|
||||
0x0bec81837, 0x01d06db6d, 0x073c9dd43, 0x0a2405d52,
|
||||
0x01ee426b1, 0x013e87a88, 0x045e00e1a, 0x08e2a1ba3,
|
||||
0x0efeee771, 0x07db9f1ba, 0x0333b019c, 0x0e00c9308,
|
||||
0x00622f689, 0x081bba9be, 0x0fd316ec0, 0x0da2def1f,
|
||||
0x06a4945ea, 0x0f6359ec5, 0x0630bfba5, 0x0adff9610,
|
||||
0x0dd7c3d15, 0x03e728968, 0x0d74b8b49, 0x06dc94b9a,
|
||||
0x0b20f2765, 0x08041988e, 0x0272b5abc, 0x0f15cfd0d,
|
||||
0x00d729960, 0x01a2fae9a, 0x0cf3296e9, 0x03a290b05,
|
||||
0x0c3a504a6, 0x04aa31032, 0x0aadd73fd, 0x0a6790636,
|
||||
0x0f319a07f, 0x095d2d576, 0x06a61931a, 0x0ed892f8d,
|
||||
0x04ba30258, 0x0e5919b8a, 0x084f10bc5, 0x074cc3282,
|
||||
0x087890780, 0x068732cb2, 0x0f78ad447, 0x0e69573dc,
|
||||
0x0728beb36, 0x051c802a4, 0x0758de776, 0x05c6df037,
|
||||
0x06a06fb25, 0x0c4c4cf40, 0x045e58b0a, 0x0922d0480,
|
||||
0x07b51d9bb, 0x07d139ed7, 0x0f1216146, 0x0314b1efe,
|
||||
0x0084d7b08, 0x0844af3b6, 0x009e49a61, 0x0434a53b3,
|
||||
0x0b89bc367, 0x0ba0a92af, 0x0e56fe08d, 0x0310df486,
|
||||
0x04a9a69c4, 0x013a49875, 0x0bcecb5eb, 0x090098676,
|
||||
0x063a186b1, 0x07895a3a8, 0x0e2e74740, 0x0206610f0,
|
||||
0x01af249de, 0x0c86caf13, 0x0a0a09f28, 0x0daaefe51,
|
||||
0x06b74fab4, 0x0799a8893, 0x071dcc3db, 0x08e91b678,
|
||||
0x04fd05c58, 0x0d39f1956, 0x041d21e8f, 0x09214fe12,
|
||||
0x0d26d7c81, 0x0d1b4991c, 0x009917277, 0x0de60e0b1,
|
||||
0x0d535ce21, 0x09090fe6b, 0x0d2236db5, 0x0784808bd,
|
||||
0x013e6fbcb, 0x0ecb1bb25, 0x02c066d8c, 0x0dbd93a4a,
|
||||
0x09be0ff4b, 0x050460f00, 0x0e27da386, 0x0424b85d6,
|
||||
|
||||
|
|
@ -0,0 +1,513 @@
|
|||
/* Intel xeon sig f24 pf 2 from m02f2410.txt */
|
||||
0x000000001, // Header Version
|
||||
0x000000028, // Patch ID
|
||||
0x007222002, // DATE
|
||||
0x000000f27, // CPUID
|
||||
0x0f0564209, // Checksum
|
||||
0x000000001, // Loader Version
|
||||
0x000000002, // Platform ID
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x0ffffffe9,
|
||||
0x00000005e,
|
||||
0x096f907f6,
|
||||
0x0aa368f02,
|
||||
0x0886f064e,
|
||||
0x0f3432dcb,
|
||||
0x08547bcf9,
|
||||
0x047ce518c,
|
||||
0x05643cca7,
|
||||
0x06c326791,
|
||||
0x00bf0c84b,
|
||||
0x065106a54,
|
||||
0x037adae8e,
|
||||
0x0ad3b82de,
|
||||
0x0c6fef325,
|
||||
0x004d82707,
|
||||
0x0f81ec787,
|
||||
0x070c19727,
|
||||
0x02c850ed8,
|
||||
0x0775f0391,
|
||||
0x001a07b67,
|
||||
0x0f401b1de,
|
||||
0x0634e9243,
|
||||
0x019ebd8d8,
|
||||
0x0ec29bcab,
|
||||
0x08568583e,
|
||||
0x075a2b1df,
|
||||
0x0c36370a9,
|
||||
0x0413f1c33,
|
||||
0x09353f364,
|
||||
0x072af0d33,
|
||||
0x032404eba,
|
||||
0x0d5f0e2a6,
|
||||
0x08ee2cd85,
|
||||
0x008b703c4,
|
||||
0x0680b6df3,
|
||||
0x09825683b,
|
||||
0x08ddf0c2a,
|
||||
0x095ccad64,
|
||||
0x0a64dda9a,
|
||||
0x099c3fe4d,
|
||||
0x0d5758d64,
|
||||
0x077f917da,
|
||||
0x0c2724189,
|
||||
0x0ada57e8a,
|
||||
0x0cd2d1775,
|
||||
0x06ddbd0bd,
|
||||
0x0bbfa6ac0,
|
||||
0x059f16bd3,
|
||||
0x0c40b7e58,
|
||||
0x0bb6fa16b,
|
||||
0x02dd33465,
|
||||
0x00f604b3b,
|
||||
0x0904a64dc,
|
||||
0x049d0a13b,
|
||||
0x0ce8336d0,
|
||||
0x008a51a53,
|
||||
0x03343c245,
|
||||
0x0a3b41126,
|
||||
0x0ca84e4f6,
|
||||
0x0ff466927,
|
||||
0x0048f403d,
|
||||
0x0bd8f63b7,
|
||||
0x07faaef40,
|
||||
0x019e43bc4,
|
||||
0x078154a50,
|
||||
0x0f016c616,
|
||||
0x0cb8ca8c6,
|
||||
0x09ebc8695,
|
||||
0x0be6a5a56,
|
||||
0x0fdf3edbe,
|
||||
0x07d8cb85d,
|
||||
0x0ae97a6e3,
|
||||
0x030c58e42,
|
||||
0x0075cba54,
|
||||
0x01076d2b3,
|
||||
0x0a3f12c69,
|
||||
0x01cc3acc4,
|
||||
0x01648fa92,
|
||||
0x0775e436e,
|
||||
0x08a72b6e1,
|
||||
0x0b6d0de93,
|
||||
0x04954b5b1,
|
||||
0x0ec6bdf39,
|
||||
0x0e1da2ed4,
|
||||
0x034f40f66,
|
||||
0x0660b428b,
|
||||
0x0b8bd391d,
|
||||
0x037d77876,
|
||||
0x04140076c,
|
||||
0x0e5b747a4,
|
||||
0x0f3f2fb37,
|
||||
0x072b5a1f8,
|
||||
0x05fbbe341,
|
||||
0x011ff256a,
|
||||
0x0dd64b0d7,
|
||||
0x016680f3a,
|
||||
0x08b5f61e7,
|
||||
0x0a2ee9221,
|
||||
0x0152bd2af,
|
||||
0x04ba620ec,
|
||||
0x06c1d443e,
|
||||
0x0b0d80763,
|
||||
0x089c1e517,
|
||||
0x091d63a95,
|
||||
0x08e8b921f,
|
||||
0x0908ed827,
|
||||
0x0fcb35cba,
|
||||
0x054d947ff,
|
||||
0x08a0c2b74,
|
||||
0x0bd45bd3a,
|
||||
0x09364ac39,
|
||||
0x09dac3b16,
|
||||
0x04235e676,
|
||||
0x06ef32ba4,
|
||||
0x0cd856fd9,
|
||||
0x0077b5cdd,
|
||||
0x06adee885,
|
||||
0x02f47aeb7,
|
||||
0x09916e84c,
|
||||
0x0794e79e2,
|
||||
0x0576d097f,
|
||||
0x040bfedce,
|
||||
0x0486c40a7,
|
||||
0x04563c59f,
|
||||
0x0f056c288,
|
||||
0x0e4a101e9,
|
||||
0x0d51220b8,
|
||||
0x05e1603f1,
|
||||
0x07733c794,
|
||||
0x0ca42178b,
|
||||
0x07df5fe7c,
|
||||
0x0a29bc8ae,
|
||||
0x0eed467f2,
|
||||
0x056cdac4e,
|
||||
0x085cb92ec,
|
||||
0x07a82e6b0,
|
||||
0x0c99ae145,
|
||||
0x089800cff,
|
||||
0x0b5cef343,
|
||||
0x0dfea9f1c,
|
||||
0x04d452eb6,
|
||||
0x0cfb04b69,
|
||||
0x07fe696ca,
|
||||
0x0b8b23891,
|
||||
0x03ff137d5,
|
||||
0x025cfdefc,
|
||||
0x0e9bb892d,
|
||||
0x0573d5587,
|
||||
0x098af70b7,
|
||||
0x0df739670,
|
||||
0x0cad744f2,
|
||||
0x0051f787a,
|
||||
0x05509563e,
|
||||
0x0c4cb60a3,
|
||||
0x053c595fb,
|
||||
0x0d11bd8b6,
|
||||
0x0a0ecec2f,
|
||||
0x0d3f35fc5,
|
||||
0x0ba12228a,
|
||||
0x050b3f0fd,
|
||||
0x0f8df7f14,
|
||||
0x0f059aea7,
|
||||
0x0ac62b793,
|
||||
0x0aa51f0fc,
|
||||
0x02c88ed46,
|
||||
0x02a7d6824,
|
||||
0x0418fd185,
|
||||
0x061e40fa0,
|
||||
0x007ae6581,
|
||||
0x0593247f5,
|
||||
0x0f81245ce,
|
||||
0x037620f69,
|
||||
0x0fc9d05e6,
|
||||
0x0652dc4d7,
|
||||
0x072c382f4,
|
||||
0x03ee90cda,
|
||||
0x04504c157,
|
||||
0x08e72df55,
|
||||
0x0fc8b1af4,
|
||||
0x037ff6f45,
|
||||
0x00cc513cf,
|
||||
0x054787a8b,
|
||||
0x0bbf92833,
|
||||
0x00f099745,
|
||||
0x005e0b452,
|
||||
0x05fd3a676,
|
||||
0x00e292c39,
|
||||
0x0d5403793,
|
||||
0x00543c6a6,
|
||||
0x0c1d89a05,
|
||||
0x082bad4d2,
|
||||
0x0d4a2f975,
|
||||
0x06057fe9c,
|
||||
0x00af202f2,
|
||||
0x00d358945,
|
||||
0x04e2c7453,
|
||||
0x080a635da,
|
||||
0x03c3edd1a,
|
||||
0x093adc35c,
|
||||
0x0ab8df389,
|
||||
0x031326689,
|
||||
0x02f653bea,
|
||||
0x086dfac6e,
|
||||
0x0b9b20ae2,
|
||||
0x037a3dc51,
|
||||
0x06bf9b64a,
|
||||
0x00a13a704,
|
||||
0x0712c6691,
|
||||
0x0c21b67f7,
|
||||
0x04233c993,
|
||||
0x0da705da3,
|
||||
0x0a0a68cbd,
|
||||
0x0f16816e1,
|
||||
0x0950e94f5,
|
||||
0x0f187809d,
|
||||
0x047b19692,
|
||||
0x0aadceb2c,
|
||||
0x0b52f1bcb,
|
||||
0x0d1bbcc3e,
|
||||
0x0f8c485ce,
|
||||
0x0c98e5b58,
|
||||
0x095faaf79,
|
||||
0x00b409dbe,
|
||||
0x06c0f1a8f,
|
||||
0x0ed84cbaf,
|
||||
0x090e2bfe1,
|
||||
0x016c9e73a,
|
||||
0x01f63849f,
|
||||
0x02251a57b,
|
||||
0x0eaa24cd0,
|
||||
0x06e6a6b5c,
|
||||
0x0ff10e11f,
|
||||
0x050f60b43,
|
||||
0x0134005ef,
|
||||
0x06f5d4e4b,
|
||||
0x047bf86e1,
|
||||
0x047e3ead3,
|
||||
0x086485bfc,
|
||||
0x0b0f95efa,
|
||||
0x0fe6d4562,
|
||||
0x07f927c86,
|
||||
0x02968f7af,
|
||||
0x0cdff3fd7,
|
||||
0x0dc857293,
|
||||
0x0bb140fae,
|
||||
0x0ab2d163e,
|
||||
0x05c47b64e,
|
||||
0x06c2af8db,
|
||||
0x0df38b67d,
|
||||
0x0f450c2c6,
|
||||
0x00ddb889f,
|
||||
0x0c1de1cbd,
|
||||
0x0098124d7,
|
||||
0x008bb90bb,
|
||||
0x0991008fd,
|
||||
0x0173c07db,
|
||||
0x06233f455,
|
||||
0x00fbd1de5,
|
||||
0x0d34c0d63,
|
||||
0x065c89419,
|
||||
0x0c3755799,
|
||||
0x0cce3e5fe,
|
||||
0x055e6fb5d,
|
||||
0x0c924feaa,
|
||||
0x0beb5f6a9,
|
||||
0x0a0b88522,
|
||||
0x0aa953166,
|
||||
0x0e90da187,
|
||||
0x04e013df5,
|
||||
0x0e79a5f7a,
|
||||
0x0ebd33690,
|
||||
0x0d34d6e03,
|
||||
0x0622aecac,
|
||||
0x0c4b8334e,
|
||||
0x060264bf1,
|
||||
0x0a47bba13,
|
||||
0x0ced31b68,
|
||||
0x05b59af47,
|
||||
0x0dc7029b5,
|
||||
0x0174d857a,
|
||||
0x05c9369aa,
|
||||
0x0e9ead1ca,
|
||||
0x058eda3c2,
|
||||
0x08388c276,
|
||||
0x019fbca67,
|
||||
0x0af66a53d,
|
||||
0x0f162693b,
|
||||
0x0672f5bc6,
|
||||
0x0dfb03404,
|
||||
0x0d42ed4da,
|
||||
0x0bf862d14,
|
||||
0x04b9f17c2,
|
||||
0x00d5f3a0a,
|
||||
0x07f0cd537,
|
||||
0x0b5c46a98,
|
||||
0x05d41d38d,
|
||||
0x0f64a219c,
|
||||
0x0f5b59e15,
|
||||
0x02cd134d8,
|
||||
0x0966c8661,
|
||||
0x0504fb339,
|
||||
0x02edeeb3d,
|
||||
0x08385aa21,
|
||||
0x06afa7bf9,
|
||||
0x07d6f2a81,
|
||||
0x0c35be851,
|
||||
0x026f51ef8,
|
||||
0x0db447baf,
|
||||
0x074beb6fc,
|
||||
0x092e561b4,
|
||||
0x0c0a38a59,
|
||||
0x0c5d3f32b,
|
||||
0x05cf96828,
|
||||
0x029793aaf,
|
||||
0x0e461b280,
|
||||
0x0a64c77d6,
|
||||
0x08f160a3a,
|
||||
0x0c4221b60,
|
||||
0x0a81c972f,
|
||||
0x0461638ce,
|
||||
0x0d5d9b0df,
|
||||
0x0d153775e,
|
||||
0x0f8588f2f,
|
||||
0x0cf3bbdc6,
|
||||
0x0b4ae2e08,
|
||||
0x0f06d37ca,
|
||||
0x0422e04a9,
|
||||
0x056ae9418,
|
||||
0x0a03745c5,
|
||||
0x033f5b799,
|
||||
0x0ed11ecbe,
|
||||
0x0d9552be7,
|
||||
0x057a4addf,
|
||||
0x0db3b60d4,
|
||||
0x082ac7181,
|
||||
0x086e671ff,
|
||||
0x08c614373,
|
||||
0x092be4ccc,
|
||||
0x03813576e,
|
||||
0x0c41ade20,
|
||||
0x0ec37b698,
|
||||
0x007ee48be,
|
||||
0x035ee922b,
|
||||
0x0dee912df,
|
||||
0x0f358e19c,
|
||||
0x057339b4e,
|
||||
0x037e97394,
|
||||
0x0d6a3882d,
|
||||
0x04e4e6bf6,
|
||||
0x0f42dd2d3,
|
||||
0x02e073e4a,
|
||||
0x0aabc06fa,
|
||||
0x0694c9886,
|
||||
0x0003b29a9,
|
||||
0x002b2de3d,
|
||||
0x0ab86db67,
|
||||
0x030868d97,
|
||||
0x0b223fb7f,
|
||||
0x05506cbb5,
|
||||
0x0f80fe1b5,
|
||||
0x0ea2798ed,
|
||||
0x08fb3392e,
|
||||
0x0f05fbbc9,
|
||||
0x0ba81fa3a,
|
||||
0x0314aa3f2,
|
||||
0x0b65900f9,
|
||||
0x00a4ae3df,
|
||||
0x04af0aa61,
|
||||
0x05d6f941f,
|
||||
0x07f3f9ca0,
|
||||
0x03740f88c,
|
||||
0x048d28c54,
|
||||
0x0c5720e9f,
|
||||
0x079b1da77,
|
||||
0x041663d91,
|
||||
0x018fe7617,
|
||||
0x0e85d9785,
|
||||
0x086127c77,
|
||||
0x095ff39e8,
|
||||
0x02d725dd4,
|
||||
0x0427bf370,
|
||||
0x0c5498ac7,
|
||||
0x02f3e312c,
|
||||
0x08fc079d7,
|
||||
0x0913754e6,
|
||||
0x0048796dc,
|
||||
0x08c4981b6,
|
||||
0x002c4aec8,
|
||||
0x07d2b809b,
|
||||
0x09730d177,
|
||||
0x0aeb7606c,
|
||||
0x004e82b37,
|
||||
0x08aa09ee7,
|
||||
0x04e913d85,
|
||||
0x0a7bbfc36,
|
||||
0x04aea998d,
|
||||
0x0878be408,
|
||||
0x0a97f1576,
|
||||
0x014a306c4,
|
||||
0x071874f1e,
|
||||
0x0d39352ee,
|
||||
0x0014ee496,
|
||||
0x05efc521d,
|
||||
0x015625553,
|
||||
0x03541f36d,
|
||||
0x02eda2872,
|
||||
0x074784483,
|
||||
0x0c83d481b,
|
||||
0x0ebd08496,
|
||||
0x06c99f041,
|
||||
0x0059a1da5,
|
||||
0x0589f0792,
|
||||
0x0222201de,
|
||||
0x0ca209b2c,
|
||||
0x02f11fad4,
|
||||
0x048da2638,
|
||||
0x04c197f69,
|
||||
0x0eb1dc551,
|
||||
0x05905d2ee,
|
||||
0x00fc62715,
|
||||
0x07c1e2170,
|
||||
0x0983adf75,
|
||||
0x03f75fcf1,
|
||||
0x039253d5a,
|
||||
0x063d7005a,
|
||||
0x0078b84ff,
|
||||
0x01cede3c5,
|
||||
0x0451cb497,
|
||||
0x0475d396a,
|
||||
0x08df12dd0,
|
||||
0x0d177deaa,
|
||||
0x0cf044d07,
|
||||
0x0071ad974,
|
||||
0x0fdbf72c0,
|
||||
0x05d242e8d,
|
||||
0x0371d0ace,
|
||||
0x05f2e3894,
|
||||
0x09799c488,
|
||||
0x07a9ca254,
|
||||
0x03753e005,
|
||||
0x08feda5b2,
|
||||
0x011090521,
|
||||
0x02a09d3b8,
|
||||
0x091600588,
|
||||
0x06a148114,
|
||||
0x08995f3e9,
|
||||
0x0e48c6736,
|
||||
0x026a1e9d3,
|
||||
0x007966973,
|
||||
0x04fed433b,
|
||||
0x0932dbb4c,
|
||||
0x078323c3c,
|
||||
0x044cfad34,
|
||||
0x0cc9b3589,
|
||||
0x0c618aec8,
|
||||
0x05cfbae87,
|
||||
0x008bd8afb,
|
||||
0x0627537f5,
|
||||
0x08ec1f9c2,
|
||||
0x01599f101,
|
||||
0x0fbdc5c6c,
|
||||
0x0fa2a1299,
|
||||
0x0fd795bb4,
|
||||
0x01c7b1099,
|
||||
0x0fb48425b,
|
||||
0x09e8cfbab,
|
||||
0x0a0daba12,
|
||||
0x0b58dc099,
|
||||
0x0aeb5c98e,
|
||||
0x0b135dacd,
|
||||
0x0479b5fee,
|
||||
0x044176521,
|
||||
0x02ec945c3,
|
||||
0x06676039a,
|
||||
0x0404b94c4,
|
||||
0x07a2af612,
|
||||
0x049a25c93,
|
||||
0x0b68d6368,
|
||||
0x0e1ff29fa,
|
||||
0x0ce0cfd3a,
|
||||
0x0441ba46d,
|
||||
0x0f31a0b4d,
|
||||
0x07ce7423e,
|
||||
0x00ebb707c,
|
||||
0x0a20be4ee,
|
||||
0x0d72dff27,
|
||||
0x01e8ea782,
|
||||
0x0880ca3af,
|
||||
0x0e7f73ae6,
|
||||
0x04c66c3b8,
|
||||
0x03fca28af,
|
||||
0x0f4eae9a2,
|
||||
0x04f8411d8,
|
||||
0x05c04699f,
|
||||
0x0be3c49b0,
|
||||
0x066f562cf,
|
||||
0x0b62e6c85,
|
||||
0x08c0ad586,
|
||||
0x058e6a6ae,
|
||||
|
|
@ -0,0 +1,513 @@
|
|||
/* Intel xeon sig f27 pf 2 from m02f2734.txt */
|
||||
0x000000001, // Header Version
|
||||
0x000000034, // Patch ID
|
||||
0x011062002, // DATE
|
||||
0x000000f27, // CPUID
|
||||
0x01e25abf5, // Checksum
|
||||
0x000000001, // Loader Version
|
||||
0x000000002, // Platform ID
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x0ffffffe9,
|
||||
0x00000005e,
|
||||
0x096f952a6,
|
||||
0x0aa368f02,
|
||||
0x053d271e6,
|
||||
0x0f8286513,
|
||||
0x0484b4e9a,
|
||||
0x09e0c09c2,
|
||||
0x003b11314,
|
||||
0x0dfb67c98,
|
||||
0x0a2957d16,
|
||||
0x0f07f25de,
|
||||
0x0b84a2555,
|
||||
0x072ec8b35,
|
||||
0x03445c734,
|
||||
0x07744f543,
|
||||
0x0c3da0cc0,
|
||||
0x0eb36172d,
|
||||
0x08b2cf574,
|
||||
0x029c867a2,
|
||||
0x0e79dfaf0,
|
||||
0x054714bb5,
|
||||
0x0524dfb69,
|
||||
0x00df65433,
|
||||
0x00b95ec14,
|
||||
0x03dc09ca2,
|
||||
0x0584ba068,
|
||||
0x02aa558ce,
|
||||
0x08cd679c8,
|
||||
0x03b2609d0,
|
||||
0x0a06306d1,
|
||||
0x080bfa93a,
|
||||
0x0482678d8,
|
||||
0x00cdf1ce6,
|
||||
0x05ec4e912,
|
||||
0x08a19f7a6,
|
||||
0x076f215be,
|
||||
0x0577d92c2,
|
||||
0x0479cd4ba,
|
||||
0x063d1f415,
|
||||
0x05af98bc5,
|
||||
0x08889bb4f,
|
||||
0x08e70943d,
|
||||
0x0b5528299,
|
||||
0x0fd63e347,
|
||||
0x0836fcfd0,
|
||||
0x04951a701,
|
||||
0x0f4613cdb,
|
||||
0x0aa7c2f52,
|
||||
0x0a0e290c7,
|
||||
0x0f646a80b,
|
||||
0x0da5b5a03,
|
||||
0x093517b47,
|
||||
0x0553d99d1,
|
||||
0x0afac198e,
|
||||
0x0486b6c6b,
|
||||
0x04efa01d8,
|
||||
0x0dc6ce226,
|
||||
0x0dac3a149,
|
||||
0x09b7cf27f,
|
||||
0x06c6246a0,
|
||||
0x0b6055a39,
|
||||
0x0b68cc841,
|
||||
0x087b6adee,
|
||||
0x01c36edb4,
|
||||
0x03ee76d20,
|
||||
0x0dbffab67,
|
||||
0x0ed12fda6,
|
||||
0x0c1aff2f2,
|
||||
0x0c110932f,
|
||||
0x00933ccfe,
|
||||
0x058fa2281,
|
||||
0x0285d5ec1,
|
||||
0x0d05b216a,
|
||||
0x076315645,
|
||||
0x0570c5c8f,
|
||||
0x06cc52f1c,
|
||||
0x0aa977e52,
|
||||
0x0066f4e03,
|
||||
0x0812bfd2c,
|
||||
0x0bfbfd7a9,
|
||||
0x070828199,
|
||||
0x060182af7,
|
||||
0x02a04e000,
|
||||
0x030f413b7,
|
||||
0x0327cef32,
|
||||
0x0ac73aa51,
|
||||
0x07c418d9f,
|
||||
0x0f493ce0e,
|
||||
0x06c14258d,
|
||||
0x0a5e2755e,
|
||||
0x0d39f994a,
|
||||
0x0ee638b08,
|
||||
0x055d50476,
|
||||
0x09b7afc5c,
|
||||
0x05da2ed13,
|
||||
0x0b75bf9f4,
|
||||
0x02606c01d,
|
||||
0x08a1d00eb,
|
||||
0x00f73428f,
|
||||
0x0b29c4fb4,
|
||||
0x0ac13e554,
|
||||
0x0a7648fe0,
|
||||
0x0be56837b,
|
||||
0x0d34fa9ff,
|
||||
0x059c855a2,
|
||||
0x07d3cc7d7,
|
||||
0x0b5b0cb50,
|
||||
0x0e6626c0b,
|
||||
0x0f07010b7,
|
||||
0x0d8054587,
|
||||
0x001a5327a,
|
||||
0x03ceae28b,
|
||||
0x0a3bf737f,
|
||||
0x03d1a37e7,
|
||||
0x06ce48d1d,
|
||||
0x0c9d91222,
|
||||
0x042f28fae,
|
||||
0x0e8dff3e4,
|
||||
0x0fd6898d0,
|
||||
0x0e772ab47,
|
||||
0x0be452c12,
|
||||
0x0f188ee09,
|
||||
0x008edb79c,
|
||||
0x0ad4d48fb,
|
||||
0x05cb75d1d,
|
||||
0x0251f4e02,
|
||||
0x06b7bb6e3,
|
||||
0x0cada2f09,
|
||||
0x0536d74eb,
|
||||
0x0acfa627a,
|
||||
0x051e2ffd2,
|
||||
0x0e4655767,
|
||||
0x0311dbbec,
|
||||
0x01011b68a,
|
||||
0x06f6e8deb,
|
||||
0x04298665d,
|
||||
0x0c0522b3c,
|
||||
0x02c3a19dc,
|
||||
0x02c48f2ae,
|
||||
0x049bca621,
|
||||
0x0b6a747fe,
|
||||
0x0a1606c81,
|
||||
0x09b2a5318,
|
||||
0x00ac114c3,
|
||||
0x0b5b35aa0,
|
||||
0x03f4ee00d,
|
||||
0x08b427e75,
|
||||
0x0b539fcd3,
|
||||
0x0a99fba84,
|
||||
0x0821fc647,
|
||||
0x0e0ac6d6e,
|
||||
0x0912f6f88,
|
||||
0x0f2009cd8,
|
||||
0x0b32330b3,
|
||||
0x0d0b80514,
|
||||
0x06f25f157,
|
||||
0x0dba2f463,
|
||||
0x088ef17d1,
|
||||
0x0147c5f21,
|
||||
0x06e29cd75,
|
||||
0x0ec14e5d1,
|
||||
0x0dcfffd24,
|
||||
0x0ccc2c510,
|
||||
0x0e5e40798,
|
||||
0x0b24814e1,
|
||||
0x0af0cdaf2,
|
||||
0x0825cf5e2,
|
||||
0x012acac6b,
|
||||
0x0439c5f36,
|
||||
0x00c533619,
|
||||
0x08e776e71,
|
||||
0x0319b44f5,
|
||||
0x019c0b404,
|
||||
0x054111b2a,
|
||||
0x06a767513,
|
||||
0x0b16944ef,
|
||||
0x030ef18ce,
|
||||
0x085df0862,
|
||||
0x00737ff49,
|
||||
0x077fe06f2,
|
||||
0x0b2de0d2f,
|
||||
0x071625e95,
|
||||
0x0c722c5a2,
|
||||
0x003b401a9,
|
||||
0x0e8b030b4,
|
||||
0x07f9e62ab,
|
||||
0x0bff8c966,
|
||||
0x0726bfeca,
|
||||
0x06adf3831,
|
||||
0x0ab85067e,
|
||||
0x05167e87a,
|
||||
0x0b06ad00c,
|
||||
0x0dd974309,
|
||||
0x05704880d,
|
||||
0x0b7279a43,
|
||||
0x038aeda19,
|
||||
0x052f5a31f,
|
||||
0x0d66d79e2,
|
||||
0x083dad3db,
|
||||
0x0a138d066,
|
||||
0x00b4674d4,
|
||||
0x007e7dd7a,
|
||||
0x07f5c70c7,
|
||||
0x04aade5f0,
|
||||
0x04fcd220f,
|
||||
0x02ae8ab6f,
|
||||
0x06fb11f68,
|
||||
0x0bf134ecc,
|
||||
0x071d3125c,
|
||||
0x03cc3f6ba,
|
||||
0x092809507,
|
||||
0x0b4a9b236,
|
||||
0x097a2ef5f,
|
||||
0x0e20e5f23,
|
||||
0x05610bfa9,
|
||||
0x0ad16eba9,
|
||||
0x05207dfba,
|
||||
0x00caa3d20,
|
||||
0x0c57cccba,
|
||||
0x07983d15d,
|
||||
0x009ced949,
|
||||
0x0ec698959,
|
||||
0x053a4b153,
|
||||
0x063c74107,
|
||||
0x0acf58270,
|
||||
0x0bc2982cd,
|
||||
0x042bf9c41,
|
||||
0x026aff8b4,
|
||||
0x09832bd6e,
|
||||
0x034e98158,
|
||||
0x0434f0f43,
|
||||
0x0cb80ccda,
|
||||
0x0d81471b6,
|
||||
0x0bd176071,
|
||||
0x0ab13735c,
|
||||
0x04e80e2c1,
|
||||
0x0cf7815f0,
|
||||
0x0b4e6ae37,
|
||||
0x01a90c457,
|
||||
0x079426d6f,
|
||||
0x0a4ac1e2c,
|
||||
0x0f76de77b,
|
||||
0x01808cd61,
|
||||
0x0d72ea071,
|
||||
0x01f02af0e,
|
||||
0x09613b531,
|
||||
0x0e83f2e9a,
|
||||
0x099a5262a,
|
||||
0x00e8a756d,
|
||||
0x0bc229ac4,
|
||||
0x02cb1af6b,
|
||||
0x08a8720d6,
|
||||
0x0c84d2c77,
|
||||
0x08547ad96,
|
||||
0x0eb794e72,
|
||||
0x0b51119ea,
|
||||
0x01c0121ea,
|
||||
0x09f8ae83b,
|
||||
0x016459999,
|
||||
0x05c17deaf,
|
||||
0x0278a3e3b,
|
||||
0x0f2bbb704,
|
||||
0x054df1a00,
|
||||
0x0521ef94e,
|
||||
0x0d40de734,
|
||||
0x0ca5badee,
|
||||
0x0a2fe3027,
|
||||
0x02ffe3ada,
|
||||
0x01df00fb9,
|
||||
0x05feb168c,
|
||||
0x081674308,
|
||||
0x099713c0e,
|
||||
0x056aae017,
|
||||
0x0e62e68f3,
|
||||
0x0aa15163a,
|
||||
0x031ac7b10,
|
||||
0x0e6a86d9c,
|
||||
0x0a006782e,
|
||||
0x09baefc91,
|
||||
0x0111277d5,
|
||||
0x080f63a4b,
|
||||
0x0624044d6,
|
||||
0x0d91a5de5,
|
||||
0x05d0255d6,
|
||||
0x092b82310,
|
||||
0x008faf5e5,
|
||||
0x0e482ff69,
|
||||
0x00a1f1757,
|
||||
0x0dc010e34,
|
||||
0x09cd07e48,
|
||||
0x0677fcfa3,
|
||||
0x00384138d,
|
||||
0x0a104220a,
|
||||
0x05431c7ec,
|
||||
0x00e8b7efb,
|
||||
0x0f1ebcd61,
|
||||
0x097ae7029,
|
||||
0x0191ff006,
|
||||
0x04308b147,
|
||||
0x0a11e05f7,
|
||||
0x02c7cb5a4,
|
||||
0x01d345971,
|
||||
0x028d23638,
|
||||
0x0c5a7a5bb,
|
||||
0x03307c971,
|
||||
0x00d3782ae,
|
||||
0x02b798842,
|
||||
0x01fc27334,
|
||||
0x04ff82ddb,
|
||||
0x0543ba685,
|
||||
0x047732c7a,
|
||||
0x0ad094a6e,
|
||||
0x0b8ff60e4,
|
||||
0x043f9ee2f,
|
||||
0x0e9a114e8,
|
||||
0x0f036be6e,
|
||||
0x03fb488a0,
|
||||
0x0280b2d46,
|
||||
0x0b1887c58,
|
||||
0x054ae583a,
|
||||
0x0454b6ce6,
|
||||
0x0e617a2c1,
|
||||
0x0b9335ac3,
|
||||
0x072361e12,
|
||||
0x0c856637a,
|
||||
0x0741b6cbe,
|
||||
0x0cf1f6f25,
|
||||
0x09f405fff,
|
||||
0x0d2525b02,
|
||||
0x022d8b05a,
|
||||
0x016860f11,
|
||||
0x0b02983e9,
|
||||
0x0388b9c2c,
|
||||
0x0196cb2f2,
|
||||
0x0fca5f1a2,
|
||||
0x09e60965d,
|
||||
0x05bed99ff,
|
||||
0x059e361fc,
|
||||
0x09361bde8,
|
||||
0x0a1527365,
|
||||
0x03f300237,
|
||||
0x0b0f5e2b8,
|
||||
0x08fb00a40,
|
||||
0x071cb9744,
|
||||
0x03327e8d3,
|
||||
0x0e89994d4,
|
||||
0x03987e389,
|
||||
0x028c6d8f7,
|
||||
0x0b2ba9fc4,
|
||||
0x0df109e0e,
|
||||
0x0622634b2,
|
||||
0x04904a82e,
|
||||
0x0576c3c2f,
|
||||
0x0e95eae46,
|
||||
0x0fb773013,
|
||||
0x0f98b91de,
|
||||
0x04edc30d5,
|
||||
0x0c6e60080,
|
||||
0x0ebefab96,
|
||||
0x0d7684df2,
|
||||
0x09cd2c3e1,
|
||||
0x0d433902a,
|
||||
0x07b9aa9eb,
|
||||
0x03c99cbaa,
|
||||
0x05a0fa53d,
|
||||
0x077297830,
|
||||
0x0869db621,
|
||||
0x0aee2d56a,
|
||||
0x02ce907c1,
|
||||
0x00aa5097c,
|
||||
0x0662e7862,
|
||||
0x0a5bfbc61,
|
||||
0x02610f3bf,
|
||||
0x03a741265,
|
||||
0x099a5836d,
|
||||
0x0edb5f89a,
|
||||
0x03ef2cfd7,
|
||||
0x00deebc49,
|
||||
0x0b3893f47,
|
||||
0x0b39982ac,
|
||||
0x0221eac08,
|
||||
0x054b5a11d,
|
||||
0x05cb8e784,
|
||||
0x087d5ac86,
|
||||
0x053fb0b32,
|
||||
0x0376b6284,
|
||||
0x0f2e4aca9,
|
||||
0x06fa350de,
|
||||
0x001453f3e,
|
||||
0x07184b158,
|
||||
0x01131e78b,
|
||||
0x0940b0d72,
|
||||
0x0abcd4431,
|
||||
0x01bb39e9a,
|
||||
0x02dd67c00,
|
||||
0x0f4babbf1,
|
||||
0x04e147ca1,
|
||||
0x061392a2f,
|
||||
0x0b5525e72,
|
||||
0x0307bc08c,
|
||||
0x00093e50a,
|
||||
0x0a3094d73,
|
||||
0x0c7aa3e29,
|
||||
0x002386d30,
|
||||
0x0a92b57e8,
|
||||
0x06ef5c157,
|
||||
0x01c3c25ac,
|
||||
0x03157eaa5,
|
||||
0x019c3aca2,
|
||||
0x07a76bba3,
|
||||
0x0d814aa5e,
|
||||
0x091716fbe,
|
||||
0x0dbcdbe3c,
|
||||
0x06f339fab,
|
||||
0x0a3f1e4da,
|
||||
0x088a1c0df,
|
||||
0x0d78cd414,
|
||||
0x0a95904cf,
|
||||
0x0d0f8b595,
|
||||
0x0b9626711,
|
||||
0x034052c93,
|
||||
0x0b398c7dc,
|
||||
0x05a029110,
|
||||
0x01421800a,
|
||||
0x0aeb25765,
|
||||
0x0bbfafe68,
|
||||
0x0d80c81f1,
|
||||
0x02fb99b5c,
|
||||
0x0ec68948a,
|
||||
0x0f5b33177,
|
||||
0x09b3196fa,
|
||||
0x04c054a2c,
|
||||
0x01283d6e1,
|
||||
0x034a029a7,
|
||||
0x0044c77ba,
|
||||
0x0775506cd,
|
||||
0x08cf19e0c,
|
||||
0x0fb249f8b,
|
||||
0x011e8ae8d,
|
||||
0x0e480faf2,
|
||||
0x0bcbf0c49,
|
||||
0x0f6d3bb3c,
|
||||
0x02fe733fb,
|
||||
0x089fdfec1,
|
||||
0x0362b1aab,
|
||||
0x0f53c7d89,
|
||||
0x00dc435be,
|
||||
0x089c41440,
|
||||
0x09d877824,
|
||||
0x00f116cbb,
|
||||
0x0f6934124,
|
||||
0x0b5f7e7bc,
|
||||
0x0d8f0faf7,
|
||||
0x0977186f0,
|
||||
0x085359865,
|
||||
0x0bba92d0d,
|
||||
0x0ca93229d,
|
||||
0x00c3a3454,
|
||||
0x063d62ec8,
|
||||
0x0c5a8861b,
|
||||
0x0f2d658a6,
|
||||
0x02482c709,
|
||||
0x0b567f38f,
|
||||
0x0395c8d02,
|
||||
0x0f1ce954c,
|
||||
0x080a0f97a,
|
||||
0x039e9a636,
|
||||
0x0c5ae1e48,
|
||||
0x06e6cc542,
|
||||
0x079abfdda,
|
||||
0x07bc66e32,
|
||||
0x0a7d822cf,
|
||||
0x04e2e83e3,
|
||||
0x07c270c9b,
|
||||
0x086cdd198,
|
||||
0x028f90f64,
|
||||
0x012048f34,
|
||||
0x0a4359214,
|
||||
0x0269d80b0,
|
||||
0x070bd0fd1,
|
||||
0x0250405f0,
|
||||
0x0258411f4,
|
||||
0x0f4055035,
|
||||
0x0df304b75,
|
||||
0x06c42bbe7,
|
||||
0x0d571b366,
|
||||
0x09ec59e75,
|
||||
0x0fa389422,
|
||||
0x073bb8104,
|
||||
0x04d6e27ee,
|
||||
0x07079a223,
|
||||
0x06a222651,
|
||||
0x0145557aa,
|
||||
0x0c2fa3440,
|
||||
0x0823b5d37,
|
||||
0x0a32cfcba,
|
||||
0x08f1cf0b4,
|
||||
0x0e9547828,
|
||||
0x0e5fa5edd,
|
||||
|
|
@ -0,0 +1,513 @@
|
|||
/* Intel xeon sig f29 pf 2 from m02f2918.txt */
|
||||
0x000000001, // Header Version
|
||||
0x000000018, // Patch ID
|
||||
0x007182003, // DATE
|
||||
0x000000f29, // CPUID
|
||||
0x00e0b85c7, // Checksum
|
||||
0x000000001, // Loader Version
|
||||
0x000000002, // Platform ID
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x000000000, // reserved
|
||||
0x03329bed4,
|
||||
0x0074ca74b,
|
||||
0x076a4c9be,
|
||||
0x0b3d0ac3b,
|
||||
0x059c1ebd3,
|
||||
0x09d06facf,
|
||||
0x0a272f2b8,
|
||||
0x0185d2aed,
|
||||
0x0d79b2394,
|
||||
0x086f96353,
|
||||
0x00b212cc9,
|
||||
0x0923bf0b8,
|
||||
0x0854956f8,
|
||||
0x0bc5754f3,
|
||||
0x0047a6840,
|
||||
0x0a548499f,
|
||||
0x08bb8c3d2,
|
||||
0x007136d29,
|
||||
0x084655796,
|
||||
0x085dc2f78,
|
||||
0x005b97d28,
|
||||
0x0baae9586,
|
||||
0x0f0a8fe9d,
|
||||
0x002d23e93,
|
||||
0x0d9065365,
|
||||
0x063898d0a,
|
||||
0x03380e625,
|
||||
0x0bd8ff455,
|
||||
0x0d71f8959,
|
||||
0x0e52d4c0d,
|
||||
0x0f5dec8dc,
|
||||
0x05155694d,
|
||||
0x07f1dc433,
|
||||
0x0984baac7,
|
||||
0x09307941a,
|
||||
0x0ebba222b,
|
||||
0x04c4eddf7,
|
||||
0x0ea59b24d,
|
||||
0x0d40dd91e,
|
||||
0x0b4be5361,
|
||||
0x013a60e39,
|
||||
0x062f71414,
|
||||
0x006ac1ec3,
|
||||
0x0f16fa69f,
|
||||
0x079e1b1a6,
|
||||
0x0caeb6bf7,
|
||||
0x0e3968588,
|
||||
0x067f9dfda,
|
||||
0x0a699431d,
|
||||
0x01ffeaa9a,
|
||||
0x06a222551,
|
||||
0x0edc5ecaf,
|
||||
0x0ff705e90,
|
||||
0x06335836e,
|
||||
0x0e1230c08,
|
||||
0x06352644b,
|
||||
0x06f3459f4,
|
||||
0x0513ac31b,
|
||||
0x059ac2e3e,
|
||||
0x076358db9,
|
||||
0x099a52964,
|
||||
0x09b58f026,
|
||||
0x0725a1ab3,
|
||||
0x02cf8d82d,
|
||||
0x0911346c5,
|
||||
0x062fed2e0,
|
||||
0x04fdb6412,
|
||||
0x0b1fce704,
|
||||
0x0ac4475d1,
|
||||
0x0f4365cad,
|
||||
0x0c9522b51,
|
||||
0x06be394be,
|
||||
0x066a34ccb,
|
||||
0x0e606a479,
|
||||
0x0a9551e8a,
|
||||
0x0e7bd89cf,
|
||||
0x081139437,
|
||||
0x036e68496,
|
||||
0x02e964e97,
|
||||
0x0e83ea910,
|
||||
0x08951b1d2,
|
||||
0x03771f8d7,
|
||||
0x08f43b11e,
|
||||
0x078298c2a,
|
||||
0x0a19b40bf,
|
||||
0x02b59f3dd,
|
||||
0x09f599f82,
|
||||
0x06d4bb01a,
|
||||
0x0b969ccdc,
|
||||
0x063600cf7,
|
||||
0x0d62993f9,
|
||||
0x0cf33b852,
|
||||
0x0297684f9,
|
||||
0x09a5366f0,
|
||||
0x0a85a510c,
|
||||
0x0cbd8e598,
|
||||
0x096f94325,
|
||||
0x0daffd9a9,
|
||||
0x08dc23c89,
|
||||
0x0faf9250a,
|
||||
0x002f8b10b,
|
||||
0x00c09b5cb,
|
||||
0x05c1d61bb,
|
||||
0x0da89a826,
|
||||
0x0e3bc0725,
|
||||
0x0f61d8f65,
|
||||
0x012b46a9a,
|
||||
0x0200957f6,
|
||||
0x00da79d3f,
|
||||
0x06711092c,
|
||||
0x0fb84416b,
|
||||
0x0ffbe8fc1,
|
||||
0x011a3dd10,
|
||||
0x0adce95e8,
|
||||
0x0fe9baacc,
|
||||
0x06b8ec8a4,
|
||||
0x0f2a1e5c3,
|
||||
0x0d56ab549,
|
||||
0x00859a811,
|
||||
0x0abcbdb26,
|
||||
0x0af788ce1,
|
||||
0x0ea8d82fe,
|
||||
0x03eca203a,
|
||||
0x0e9dd69c8,
|
||||
0x00baebdcf,
|
||||
0x0003276e8,
|
||||
0x09c50beb4,
|
||||
0x0dbc83b67,
|
||||
0x0bad24e29,
|
||||
0x0f9fd719a,
|
||||
0x065a3362e,
|
||||
0x03b7d4bd4,
|
||||
0x0a0c265f5,
|
||||
0x07634cee9,
|
||||
0x00f768f1b,
|
||||
0x0da01e841,
|
||||
0x08e4cec81,
|
||||
0x0b64af8cb,
|
||||
0x0ad5d20fa,
|
||||
0x068cd9345,
|
||||
0x0d98a7739,
|
||||
0x0ec42b0ae,
|
||||
0x074ef6ebb,
|
||||
0x0b72df903,
|
||||
0x0c2575fed,
|
||||
0x0e996d597,
|
||||
0x0d17bbee4,
|
||||
0x0e59c6594,
|
||||
0x02fb7914f,
|
||||
0x016daeb9a,
|
||||
0x02594ff1e,
|
||||
0x0de03f3bf,
|
||||
0x0b4b8e9ec,
|
||||
0x0e145693d,
|
||||
0x0f80ebb0c,
|
||||
0x03ab77011,
|
||||
0x016f883e2,
|
||||
0x05f8afaf2,
|
||||
0x0ab3407e5,
|
||||
0x0e50ad4de,
|
||||
0x0136099ab,
|
||||
0x099e96e09,
|
||||
0x0f8de926d,
|
||||
0x0409453d8,
|
||||
0x01da14466,
|
||||
0x0e2a19832,
|
||||
0x088c9bf9e,
|
||||
0x0970810b1,
|
||||
0x0f60b3ca5,
|
||||
0x0b09ae791,
|
||||
0x0e7409020,
|
||||
0x0ff5caf65,
|
||||
0x03613105d,
|
||||
0x07758e647,
|
||||
0x04ea9cb40,
|
||||
0x0af5a7c9a,
|
||||
0x02aced763,
|
||||
0x0eeb02a1c,
|
||||
0x022c3092f,
|
||||
0x04b805b32,
|
||||
0x0372bc093,
|
||||
0x0c25a85ae,
|
||||
0x065715cb3,
|
||||
0x0d12c469b,
|
||||
0x0e2a83a87,
|
||||
0x03757f955,
|
||||
0x02ff422bf,
|
||||
0x0f35c618f,
|
||||
0x0827fca84,
|
||||
0x0dd519318,
|
||||
0x0dee4ebf0,
|
||||
0x0114ab35e,
|
||||
0x0e2c7ed56,
|
||||
0x067d4d66d,
|
||||
0x01bba167b,
|
||||
0x0cf54d370,
|
||||
0x059c3befc,
|
||||
0x0805e8928,
|
||||
0x046970761,
|
||||
0x076d199c3,
|
||||
0x0e607fe0b,
|
||||
0x0d0e76651,
|
||||
0x0cb59835e,
|
||||
0x084173ed2,
|
||||
0x024cd7d6b,
|
||||
0x0cb3c23cc,
|
||||
0x097cfdc89,
|
||||
0x0ce55887d,
|
||||
0x0c3562057,
|
||||
0x03c79ea38,
|
||||
0x031b95d11,
|
||||
0x0cc6a29c3,
|
||||
0x01a2e3a6d,
|
||||
0x0d81f86e9,
|
||||
0x00ebfe35e,
|
||||
0x028efd0a6,
|
||||
0x03158ff42,
|
||||
0x035aa61eb,
|
||||
0x0724c40d3,
|
||||
0x0cf0e6ffa,
|
||||
0x06cc9a9bb,
|
||||
0x0e27ad39d,
|
||||
0x02dfafc10,
|
||||
0x030891d55,
|
||||
0x0e2514225,
|
||||
0x0ee329e1f,
|
||||
0x0f4430f11,
|
||||
0x0e281e729,
|
||||
0x01c30b184,
|
||||
0x08c71c29b,
|
||||
0x01db9a543,
|
||||
0x0edfad515,
|
||||
0x0071532b1,
|
||||
0x068251089,
|
||||
0x070cc3e04,
|
||||
0x0b7c5c7fd,
|
||||
0x03fc4f321,
|
||||
0x0c24893ad,
|
||||
0x0e68273f5,
|
||||
0x069cf0691,
|
||||
0x0c6794d67,
|
||||
0x02acd766f,
|
||||
0x07426d7b2,
|
||||
0x0df336ffa,
|
||||
0x09e63e3fd,
|
||||
0x0ec080c9f,
|
||||
0x027826e24,
|
||||
0x00d38caab,
|
||||
0x0e4c78756,
|
||||
0x0dc24d7f2,
|
||||
0x02b9e488b,
|
||||
0x0dcec3e72,
|
||||
0x0867536fe,
|
||||
0x0abde994d,
|
||||
0x0cf267957,
|
||||
0x0e3b33aa2,
|
||||
0x0900836a8,
|
||||
0x0605564d4,
|
||||
0x0e5006b9a,
|
||||
0x0a2655683,
|
||||
0x00da56c2e,
|
||||
0x0f08b8e9c,
|
||||
0x06767940e,
|
||||
0x0640f781e,
|
||||
0x03840e0d6,
|
||||
0x079fc3a8d,
|
||||
0x0a54a1961,
|
||||
0x0ec16340f,
|
||||
0x057bf0c61,
|
||||
0x09082e9a7,
|
||||
0x0c7264e5a,
|
||||
0x07df38c2f,
|
||||
0x07a5c1c67,
|
||||
0x0d5715872,
|
||||
0x06537508f,
|
||||
0x085316c41,
|
||||
0x065d908ba,
|
||||
0x08c377ce1,
|
||||
0x0920bf34e,
|
||||
0x0c3a5fddd,
|
||||
0x050c46a39,
|
||||
0x0744ebffa,
|
||||
0x02e289f15,
|
||||
0x0abe2d4b2,
|
||||
0x0eed6f10c,
|
||||
0x0d07dda7c,
|
||||
0x0ba12b57a,
|
||||
0x06fe894c4,
|
||||
0x06f38610f,
|
||||
0x0240ce1a5,
|
||||
0x066f0ec19,
|
||||
0x0e8ff8ca9,
|
||||
0x02c6213e6,
|
||||
0x0e3a4f1d1,
|
||||
0x0635c8eb1,
|
||||
0x0357d4a4e,
|
||||
0x0dbe916d2,
|
||||
0x0f0a31cff,
|
||||
0x053ba740a,
|
||||
0x0d20dd392,
|
||||
0x00ee452af,
|
||||
0x0b5c14d17,
|
||||
0x019e70471,
|
||||
0x0f12ef4dd,
|
||||
0x0f759fd85,
|
||||
0x04ce679af,
|
||||
0x06eeb689b,
|
||||
0x09a96db15,
|
||||
0x0b1a87685,
|
||||
0x0c4bf146b,
|
||||
0x0ee7711a1,
|
||||
0x06dee66e1,
|
||||
0x0cc07fe31,
|
||||
0x03381bb8b,
|
||||
0x0526c5927,
|
||||
0x0da79a123,
|
||||
0x00414480a,
|
||||
0x0d0fb99b9,
|
||||
0x0ade3682c,
|
||||
0x03a783bdf,
|
||||
0x0110d8965,
|
||||
0x0f814b52d,
|
||||
0x075add544,
|
||||
0x0d65c42a8,
|
||||
0x0f035fa90,
|
||||
0x02d87a12e,
|
||||
0x0b9ef5f9b,
|
||||
0x0d36ec2db,
|
||||
0x03518bc58,
|
||||
0x0d6afc7d8,
|
||||
0x0cc3bc865,
|
||||
0x032cba2f5,
|
||||
0x0e74c6724,
|
||||
0x0e03f2e96,
|
||||
0x058a9d15a,
|
||||
0x0d2033865,
|
||||
0x04470e293,
|
||||
0x0ae63a8b1,
|
||||
0x063560a03,
|
||||
0x0fc9418a4,
|
||||
0x0b2a81e9d,
|
||||
0x07513002a,
|
||||
0x0185a1324,
|
||||
0x09338517b,
|
||||
0x0ae5db469,
|
||||
0x0c8c399e9,
|
||||
0x0d66aad92,
|
||||
0x04007b0d0,
|
||||
0x0ea6574f3,
|
||||
0x0b73d78f3,
|
||||
0x0a6e0604f,
|
||||
0x0c13ae042,
|
||||
0x05eafb097,
|
||||
0x04a7c2731,
|
||||
0x01068d9c5,
|
||||
0x08d324a61,
|
||||
0x07142004b,
|
||||
0x0e4295abf,
|
||||
0x018ce86c9,
|
||||
0x043bc75bf,
|
||||
0x0468a3c36,
|
||||
0x013af562c,
|
||||
0x0651b3dc2,
|
||||
0x0c83fbdad,
|
||||
0x0102e9e9a,
|
||||
0x0fcbf1a1a,
|
||||
0x06f19d68d,
|
||||
0x00c9a231e,
|
||||
0x06081f2fc,
|
||||
0x0c1b6d890,
|
||||
0x0622baecb,
|
||||
0x0e2170084,
|
||||
0x03a8de255,
|
||||
0x0de806767,
|
||||
0x064202cb8,
|
||||
0x0ca531f76,
|
||||
0x03a7daf7b,
|
||||
0x02a9c50c4,
|
||||
0x03bff38d4,
|
||||
0x0e377aeb0,
|
||||
0x06e52a44c,
|
||||
0x0da43c5b9,
|
||||
0x060488151,
|
||||
0x010189859,
|
||||
0x0e9317dda,
|
||||
0x0fcc22809,
|
||||
0x0b87046a1,
|
||||
0x0d93ad01b,
|
||||
0x0ac234692,
|
||||
0x070e5510d,
|
||||
0x06a7716b2,
|
||||
0x0522e3d28,
|
||||
0x063c58530,
|
||||
0x0416d8f72,
|
||||
0x0c0380627,
|
||||
0x062dc80cf,
|
||||
0x0475038d3,
|
||||
0x08f53ab9d,
|
||||
0x0bd2c7049,
|
||||
0x092c23223,
|
||||
0x03bc37d70,
|
||||
0x0d43b29ac,
|
||||
0x00b216221,
|
||||
0x0dcb983c6,
|
||||
0x0711a19d1,
|
||||
0x02d382316,
|
||||
0x06b242aa7,
|
||||
0x05fde5d00,
|
||||
0x0bdc5f1e5,
|
||||
0x0810d17e3,
|
||||
0x0b63c663b,
|
||||
0x03a8c18eb,
|
||||
0x017abff77,
|
||||
0x04900b01a,
|
||||
0x0d80067f8,
|
||||
0x0969e0260,
|
||||
0x04e657591,
|
||||
0x050590503,
|
||||
0x08ff18b94,
|
||||
0x007575bf3,
|
||||
0x0080cab76,
|
||||
0x0b9b9d6f1,
|
||||
0x0ad6a4dad,
|
||||
0x00f534392,
|
||||
0x0b866441e,
|
||||
0x0deb6d2ee,
|
||||
0x0c7f0e213,
|
||||
0x0cfa7f497,
|
||||
0x0303a32f4,
|
||||
0x0c407e838,
|
||||
0x0eb65cce1,
|
||||
0x01416ad8b,
|
||||
0x04fa2a498,
|
||||
0x0ce06724d,
|
||||
0x07674ed6e,
|
||||
0x086587ea9,
|
||||
0x05af951f0,
|
||||
0x02e03b991,
|
||||
0x04ae8b441,
|
||||
0x0e5aa5fdb,
|
||||
0x059104c1f,
|
||||
0x04c3389b4,
|
||||
0x0c7225e04,
|
||||
0x0e76d7adf,
|
||||
0x01be6bce6,
|
||||
0x023536151,
|
||||
0x0577c4a93,
|
||||
0x0cf20768e,
|
||||
0x0d0a15a40,
|
||||
0x0deae556e,
|
||||
0x0ce4909cf,
|
||||
0x036fe8c50,
|
||||
0x02f125042,
|
||||
0x02051dced,
|
||||
0x0e3048c09,
|
||||
0x0cbe64203,
|
||||
0x0080eef19,
|
||||
0x0ea7a3015,
|
||||
0x0cc558219,
|
||||
0x09f3676d6,
|
||||
0x02bc02a0c,
|
||||
0x0e1e5b3c4,
|
||||
0x0c4bfadbc,
|
||||
0x05ad6f272,
|
||||
0x078e69aa9,
|
||||
0x0ad8f959d,
|
||||
0x0b372cc9b,
|
||||
0x07f0b3e76,
|
||||
0x09fc4bdfe,
|
||||
0x04b40fb2f,
|
||||
0x03b4f00a7,
|
||||
0x04a10fdae,
|
||||
0x0acfcea26,
|
||||
0x0595d7ef8,
|
||||
0x0da34e8ad,
|
||||
0x0adc285e2,
|
||||
0x0d3fe31b0,
|
||||
0x061ca77c5,
|
||||
0x0c1b795f9,
|
||||
0x0da8aaff9,
|
||||
0x0eb54735a,
|
||||
0x0946fa909,
|
||||
0x0485b696a,
|
||||
0x090ac554e,
|
||||
0x083d2a0cd,
|
||||
0x0c49f5f6c,
|
||||
0x0f370b606,
|
||||
0x08ef2e6db,
|
||||
0x06b48d5b1,
|
||||
0x0bab3d7f4,
|
||||
0x0b8958ae4,
|
||||
0x0f73e1619,
|
||||
0x03835ee1a,
|
||||
0x0824f77b5,
|
||||
0x062adcb8d,
|
||||
0x0cf229251,
|
||||
0x0a60ade9e,
|
||||
0x0fa643142,
|
||||
0x069d27040,
|
||||
0x0c87c327f,
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/chip.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <cpu/intel/microcode.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
|
||||
/* 512KB cache */
|
||||
static uint32_t microcode_updates[] = {
|
||||
/* WARNING - Intel has a new data structure that has variable length
|
||||
* microcode update lengths. They are encoded in int 8 and 9. A
|
||||
* dummy header of nulls must terminate the list.
|
||||
*/
|
||||
#include "microcode_m02f2203.h"
|
||||
#include "microcode_m02f2410.h"
|
||||
//#include "microcode_m02f2728.h"
|
||||
#include "microcode_m02f2734.h"
|
||||
#include "microcode_m02f2918.h"
|
||||
/* Dummy terminator */
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
};
|
||||
|
||||
|
||||
static void model_f2x_init(device_t dev)
|
||||
{
|
||||
/* Turn on caching if we haven't already */
|
||||
x86_enable_cache();
|
||||
x86_setup_mtrrs();
|
||||
x86_mtrr_check();
|
||||
|
||||
/* Update the microcode */
|
||||
intel_update_microcode(microcode_updates);
|
||||
|
||||
/* Enable the local cpu apics */
|
||||
setup_lapic();
|
||||
|
||||
/* Start up my cpu siblings */
|
||||
intel_sibling_init(cpu);
|
||||
};
|
||||
|
||||
static struct device_operations cpu_dev_ops = {
|
||||
.init = model_f1x_init,
|
||||
};
|
||||
static struct cpu_device_id cpu_table[] = {
|
||||
{ X86_VENDOR_INTEL, 0x0f22 },
|
||||
{ X86_VENDOR_INTEL, 0x0f24 },
|
||||
{ X86_VENDOR_INTEL, 0x0f27 },
|
||||
{ X86_VENDOR_INTEL, 0x0f29 },
|
||||
// { X86_VENDOR_INTEL, 0x0f25 }, /* I don't have a microcode update for this cpu */
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static struct cpu_driver driver __cpu_driver = {
|
||||
.ops = &cpu_dev_ops,
|
||||
.id_table = cpu_table,
|
||||
};
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
dir /cpu/x86/tsc
|
||||
dir /cpu/x86/mtrr
|
||||
dir /cpu/x86/fpu
|
||||
dir /cpu/x86/mmx
|
||||
dir /cpu/x86/sse
|
||||
dir /cpu/x86/lapic
|
||||
dir /cpu/x86/cache
|
||||
dir /cpu/intel/microcode
|
||||
dir /cpu/intel/hyperthreading
|
||||
driver model_f3x_init.o
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,59 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/chip.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <cpu/intel/microcode.h>
|
||||
#include <cpu/intel/hyperthreading.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
|
||||
static uint32_t microcode_updates[] = {
|
||||
/* WARNING - Intel has a new data structure that has variable length
|
||||
* microcode update lengths. They are encoded in int 8 and 9. A
|
||||
* dummy header of nulls must terminate the list.
|
||||
*/
|
||||
|
||||
#include "microcode_M1DF3413.h"
|
||||
/* Dummy terminator */
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0,
|
||||
};
|
||||
|
||||
|
||||
static void model_f3x_init(device_t cpu)
|
||||
{
|
||||
/* Turn on caching if we haven't already */
|
||||
x86_enable_cache();
|
||||
x86_setup_mtrrs();
|
||||
x86_mtrr_check();
|
||||
|
||||
/* Update the microcode */
|
||||
intel_update_microcode(microcode_updates);
|
||||
|
||||
/* Enable the local cpu apics */
|
||||
setup_lapic();
|
||||
|
||||
/* Start up my cpu siblings */
|
||||
intel_sibling_init(cpu);
|
||||
};
|
||||
|
||||
static struct device_operations cpu_dev_ops = {
|
||||
.init = model_f3x_init,
|
||||
};
|
||||
static struct cpu_device_id cpu_table[] = {
|
||||
{ X86_VENDOR_INTEL, 0x0f34 }, /* Xeon */
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static struct cpu_driver model_f3x __cpu_driver = {
|
||||
.ops = &cpu_dev_ops,
|
||||
.id_table = cpu_table,
|
||||
};
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
config chip.h
|
||||
object slot_2.o
|
||||
dir /cpu/intel/model_6xx
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
extern struct chip_control cpu_intel_slot_2_control;
|
||||
|
||||
struct cpu_intel_slot_2_config {
|
||||
};
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#include <device/chip.h>
|
||||
#include "chip.h"
|
||||
|
||||
|
||||
struct chip_control cpu_intel_slot_2_control = {
|
||||
.name = "slot 2",
|
||||
};
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
config chip.h
|
||||
object socket_mPGA603_400Mhz.o
|
||||
dir /cpu/intel/model_f0x
|
||||
dir /cpu/intel/model_f1x
|
||||
dir /cpu/intel/model_f2x
|
||||
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
extern struct chip_control cpu_intel_socket_mPGA603_400Mhz_control;
|
||||
|
||||
struct cpu_intel_socket_mPGA603_400Mhz_config {
|
||||
};
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#include <device/chip.h>
|
||||
#include "chip.h"
|
||||
|
||||
|
||||
struct chip_control cpu_intel_socket_mPGA603_400Mhz_control = {
|
||||
.name = "socket mPGA603_400Mhz",
|
||||
};
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
config chip.h
|
||||
object socket_mPGA604_533Mhz.o
|
||||
dir /cpu/intel/model_f2x
|
||||
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
extern struct chip_control cpu_intel_socket_mPGA604_533Mhz_control;
|
||||
|
||||
struct cpu_intel_socket_mPGA604_533Mhz_config {
|
||||
};
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#include <device/chip.h>
|
||||
#include "chip.h"
|
||||
|
||||
|
||||
struct chip_control cpu_intel_socket_mPGA604_533Mhz_control = {
|
||||
.name = "socket mPGA604_533Mhz",
|
||||
};
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
config chip.h
|
||||
object socket_mPGA604_800Mhz.o
|
||||
dir /cpu/intel/model_f3x
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
extern struct chip_control cpu_intel_socket_mPGA604_800Mhz_control;
|
||||
|
||||
struct cpu_intel_socket_mPGA604_800Mhz_config {
|
||||
};
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#include <device/chip.h>
|
||||
#include "chip.h"
|
||||
|
||||
|
||||
struct chip_control cpu_intel_socket_mPGA604_800Mhz_control = {
|
||||
.name = "socket mPGA604_800Mhz",
|
||||
};
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
#define THERMAL_MONITORING_OFF 0
|
||||
#define THERMAL_MONITORING_SET 0x00000008
|
||||
#define MISC_ENABLE 0x01a0
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
#define THERMAL_MONITORING_OFF 0
|
||||
#define THERMAL_MONITORING_SET 0x00000008
|
||||
#define MISC_ENABLE 0x01a0
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
/*
|
||||
This software and ancillary information (herein called SOFTWARE )
|
||||
called LinuxBIOS is made available under the terms described
|
||||
here. The SOFTWARE has been approved for release with associated
|
||||
LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
|
||||
been authored by an employee or employees of the University of
|
||||
California, operator of the Los Alamos National Laboratory under
|
||||
Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
|
||||
U.S. Government has rights to use, reproduce, and distribute this
|
||||
SOFTWARE. The public may copy, distribute, prepare derivative works
|
||||
and publicly display this SOFTWARE without charge, provided that this
|
||||
Notice and any statement of authorship are reproduced on all copies.
|
||||
Neither the Government nor the University makes any warranty, express
|
||||
or implied, or assumes any liability or responsibility for the use of
|
||||
this SOFTWARE. If SOFTWARE is modified to produce derivative works,
|
||||
such modified SOFTWARE should be clearly marked, so as not to confuse
|
||||
it with the version available from LANL.
|
||||
*/
|
||||
/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
|
||||
* rminnich@lanl.gov
|
||||
*/
|
||||
|
||||
|
||||
/** Start code to put an i386 or later processor into 32-bit
|
||||
* protected mode.
|
||||
*/
|
||||
|
||||
/* .section ".rom.text" */
|
||||
#include <arch/rom_segs.h>
|
||||
.code16
|
||||
.globl _start
|
||||
.type _start, @function
|
||||
|
||||
_start:
|
||||
cli
|
||||
/* Save the BIST result */
|
||||
movl %eax, %ebp
|
||||
|
||||
/* thanks to kmliu@sis.tw.com for this TBL fix ... */
|
||||
/**/
|
||||
/* IMMEDIATELY invalidate the translation lookaside buffer before executing*/
|
||||
/* any further code. Even though paging is disabled we could still get*/
|
||||
/*false address translations due to the TLB if we didn't invalidate it.*/
|
||||
/**/
|
||||
xorl %eax, %eax
|
||||
movl %eax, %cr3 /* Invalidate TLB*/
|
||||
|
||||
|
||||
/* Invalidating the cache here seems to be a bad idea on
|
||||
* modern processors. Don't.
|
||||
* If we are hyperthreaded or we have multiple cores it is bad,
|
||||
* for SMP startup. On Opterons it causes a 5 second delay.
|
||||
* Invalidating the cache was pure paranoia in any event.
|
||||
* If you cpu needs it you can write a cpu dependent version of
|
||||
* entry16.inc.
|
||||
*/
|
||||
|
||||
/* Note: gas handles memory addresses in 16 bit code very poorly.
|
||||
* In particular it doesn't appear to have a directive allowing you
|
||||
* associate a section or even an absolute offset with a segment register.
|
||||
*
|
||||
* This means that anything except cs:ip relative offsets are
|
||||
* a real pain in 16 bit mode. And explains why it is almost
|
||||
* imposible to get gas to do lgdt correctly.
|
||||
*
|
||||
* One way to work around this is to have the linker do the
|
||||
* math instead of the assembler. This solves the very
|
||||
* pratical problem of being able to write code that can
|
||||
* be relocated.
|
||||
*
|
||||
* An lgdt call before we have memory enabled cannot be
|
||||
* position independent, as we cannot execute a call
|
||||
* instruction to get our current instruction pointer.
|
||||
* So while this code is relocateable it isn't arbitrarily
|
||||
* relocatable.
|
||||
*
|
||||
* The criteria for relocation have been relaxed to their
|
||||
* utmost, so that we can use the same code for both
|
||||
* our initial entry point and startup of the second cpu.
|
||||
* The code assumes when executing at _start that:
|
||||
* (((cs & 0xfff) == 0) and (ip == _start & 0xffff))
|
||||
* or
|
||||
* ((cs == anything) and (ip == 0)).
|
||||
*
|
||||
* The restrictions in reset16.inc mean that _start initially
|
||||
* must be loaded at or above 0xffff0000 or below 0x100000.
|
||||
*
|
||||
* The linker scripts computs gdtptr16_offset by simply returning
|
||||
* the low 16 bits. This means that the intial segment used
|
||||
* when start is called must be 64K aligned. This should not
|
||||
* restrict the address as the ip address can be anything.
|
||||
*/
|
||||
|
||||
movw %cs, %ax
|
||||
shlw $4, %ax
|
||||
movw $gdtptr16_offset, %bx
|
||||
subw %ax, %bx
|
||||
data32 lgdt %cs:(%bx)
|
||||
|
||||
movl %cr0, %eax
|
||||
andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
|
||||
orl $0x60000001, %eax /* CD, NW, PE = 1 */
|
||||
movl %eax, %cr0
|
||||
|
||||
/* Restore BIST to %eax */
|
||||
movl %ebp, %eax
|
||||
|
||||
/* Now that we are in protected mode jump to a 32 bit code segment. */
|
||||
data32 ljmp $ROM_CODE_SEG, $__protected_start
|
||||
|
||||
/** The gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
|
||||
* at 0x18; these are Linux-compatible.
|
||||
*/
|
||||
|
||||
.align 4
|
||||
.globl gdtptr16
|
||||
gdtptr16:
|
||||
.word gdt_end - gdt -1 /* compute the table limit */
|
||||
.long gdt /* we know the offset */
|
||||
|
||||
.globl _estart
|
||||
_estart:
|
||||
.code32
|
||||
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
gdtptr16_offset = gdtptr16 & 0xffff;
|
||||
_start_offset = _start & 0xffff;
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
.section ".reset"
|
||||
.code16
|
||||
.globl reset_vector
|
||||
reset_vector:
|
||||
#if _ROMBASE >= 0xffff0000
|
||||
/* jmp _start */
|
||||
.byte 0xe9
|
||||
.int _start - ( . + 2 )
|
||||
/* Note: The above jump is hand coded to work around bugs in binutils.
|
||||
* 5 byte are used for a 3 byte instruction. This works because x86
|
||||
* is little endian and allows us to use supported 32bit relocations
|
||||
* instead of the weird 16 bit relocations that binutils does not
|
||||
* handle consistenly between versions because they are used so rarely.
|
||||
*/
|
||||
#else
|
||||
# error _ROMBASE is an unsupported value
|
||||
#endif
|
||||
. = 0x8;
|
||||
.code32
|
||||
jmp protected_start
|
||||
.previous
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* _ROMTOP : The top of the rom used where we
|
||||
* need to put the reset vector.
|
||||
*/
|
||||
|
||||
SECTIONS {
|
||||
_ROMTOP = (_ROMBASE >= 0xffff0000)? 0xfffffff0 : 0xffff0;
|
||||
. = _ROMTOP;
|
||||
.reset . : {
|
||||
*(.reset)
|
||||
. = 15 ;
|
||||
BYTE(0x00);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/* For starting linuxBIOS in protected mode */
|
||||
|
||||
#include <arch/rom_segs.h>
|
||||
|
||||
/* .section ".rom.text" */
|
||||
.code32
|
||||
|
||||
.align 4
|
||||
.globl gdtptr
|
||||
|
||||
gdt:
|
||||
gdtptr:
|
||||
.word gdt_end - gdt -1 /* compute the table limit */
|
||||
.long gdt /* we know the offset */
|
||||
.word 0
|
||||
|
||||
/* flat code segment */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x9b, 0xcf, 0x00
|
||||
|
||||
/* flat data segment */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x93, 0xcf, 0x00
|
||||
|
||||
gdt_end:
|
||||
|
||||
|
||||
/*
|
||||
* When we come here we are in protected mode. We expand
|
||||
* the stack and copies the data segment from ROM to the
|
||||
* memory.
|
||||
*
|
||||
* After that, we call the chipset bootstrap routine that
|
||||
* does what is left of the chipset initialization.
|
||||
*
|
||||
* NOTE aligned to 4 so that we are sure that the prefetch
|
||||
* cache will be reloaded.
|
||||
*/
|
||||
.align 4
|
||||
.globl protected_start
|
||||
protected_start:
|
||||
|
||||
lgdt %cs:gdtptr
|
||||
ljmp $ROM_CODE_SEG, $__protected_start
|
||||
|
||||
__protected_start:
|
||||
/* Save the BIST value */
|
||||
movl %eax, %ebp
|
||||
|
||||
intel_chip_post_macro(0x10) /* post 10 */
|
||||
|
||||
movw $ROM_DATA_SEG, %ax
|
||||
movw %ax, %ds
|
||||
movw %ax, %es
|
||||
movw %ax, %ss
|
||||
movw %ax, %fs
|
||||
movw %ax, %gs
|
||||
|
||||
/* Restore the BIST value to %eax */
|
||||
movl %ebp, %eax
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
_cache_ram_seg_base = DEFINED(CACHE_RAM_BASE)? CACHE_RAM_BASE - _rodata : 0;
|
||||
_cache_ram_seg_base_low = (_cache_ram_seg_base) & 0xffff;
|
||||
_cache_ram_seg_base_middle = (_cache_ram_seg_base >> 16) & 0xff;
|
||||
_cache_ram_seg_base_high = (_cache_ram_seg_base >> 24) & 0xff;
|
||||
|
||||
_rom_code_seg_base = _ltext - _text;
|
||||
_rom_code_seg_base_low = (_rom_code_seg_base) & 0xffff;
|
||||
_rom_code_seg_base_middle = (_rom_code_seg_base >> 16) & 0xff;
|
||||
_rom_code_seg_base_high = (_rom_code_seg_base >> 24) & 0xff;
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
.section ".reset"
|
||||
.code16
|
||||
.globl reset_vector
|
||||
reset_vector:
|
||||
|
||||
. = 0x8;
|
||||
.code32
|
||||
jmp protected_start
|
||||
|
||||
.previous
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* _ROMTOP : The top of the rom used where we
|
||||
* need to put the reset vector.
|
||||
*/
|
||||
|
||||
SECTIONS {
|
||||
_ROMTOP = _ROMBASE + ROM_IMAGE_SIZE - 0x10;
|
||||
. = _ROMTOP;
|
||||
.reset (.): {
|
||||
*(.reset)
|
||||
. = 15 ;
|
||||
BYTE(0x00);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1 @@
|
|||
object cache.o
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#include <console/console.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
|
||||
void x86_enable_cache(void)
|
||||
{
|
||||
post_code(0x60);
|
||||
printk_info("Enabling cache\n");
|
||||
enable_cache();
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/* preserve BIST in %eax */
|
||||
movl %eax, %ebp
|
||||
|
||||
/* Disable floating point emulation */
|
||||
movl %cr0, %eax
|
||||
andl $~(1<<2), %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
movl %ebp, %eax
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
object lapic.o
|
||||
object lapic_cpu_init.o
|
||||
object secondary.S
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#include <cpu/x86/msr.h>
|
||||
|
||||
int boot_cpu(void)
|
||||
{
|
||||
int bsp;
|
||||
msr_t msr;
|
||||
msr = rdmsr(0x1b);
|
||||
bsp = !!(msr.lo & (1 << 8));
|
||||
return bsp;
|
||||
}
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
|
||||
void setup_lapic(void)
|
||||
{
|
||||
/* this is so interrupts work. This is very limited scope --
|
||||
* linux will do better later, we hope ...
|
||||
*/
|
||||
/* this is the first way we learned to do it. It fails on real SMP
|
||||
* stuff. So we have to do things differently ...
|
||||
* see the Intel mp1.4 spec, page A-3
|
||||
*/
|
||||
|
||||
#if NEED_LAPIC == 1
|
||||
/* Only Pentium Pro and later have those MSR stuff */
|
||||
msr_t msr;
|
||||
|
||||
printk_info("Setting up local apic...");
|
||||
|
||||
/* Enable the local apic */
|
||||
msr = rdmsr(LAPIC_BASE_MSR);
|
||||
msr.lo |= LAPIC_BASE_MSR_ENABLE;
|
||||
msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK;
|
||||
msr.lo |= LAPIC_DEFAULT_BASE;
|
||||
wrmsr(LAPIC_BASE_MSR, msr);
|
||||
|
||||
/*
|
||||
* Set Task Priority to 'accept all'.
|
||||
*/
|
||||
lapic_write_around(LAPIC_TASKPRI,
|
||||
lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
|
||||
|
||||
/* Put the local apic in virtual wire mode */
|
||||
lapic_write_around(LAPIC_SPIV,
|
||||
(lapic_read_around(LAPIC_SPIV) & ~(LAPIC_VECTOR_MASK))
|
||||
| LAPIC_SPIV_ENABLE);
|
||||
lapic_write_around(LAPIC_LVT0,
|
||||
(lapic_read_around(LAPIC_LVT0) &
|
||||
~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
|
||||
LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
|
||||
LAPIC_SEND_PENDING |LAPIC_LVT_RESERVED_1 |
|
||||
LAPIC_DELIVERY_MODE_MASK))
|
||||
| (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING |
|
||||
LAPIC_DELIVERY_MODE_EXTINT)
|
||||
);
|
||||
lapic_write_around(LAPIC_LVT1,
|
||||
(lapic_read_around(LAPIC_LVT1) &
|
||||
~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
|
||||
LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
|
||||
LAPIC_SEND_PENDING |LAPIC_LVT_RESERVED_1 |
|
||||
LAPIC_DELIVERY_MODE_MASK))
|
||||
| (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING |
|
||||
LAPIC_DELIVERY_MODE_NMI)
|
||||
);
|
||||
|
||||
printk_debug(" apic_id: %d ", lapicid());
|
||||
|
||||
#else /* !NEED_LLAPIC */
|
||||
/* Only Pentium Pro and later have those MSR stuff */
|
||||
msr_t msr;
|
||||
|
||||
printk_info("Disabling local apic...");
|
||||
|
||||
msr = rdmsr(LAPIC_BASE_MSR);
|
||||
msr.lo &= ~LAPIC_BASE_MSR_ENABLE;
|
||||
wrmsr(LAPIC_BASE_MSR, msr);
|
||||
#endif /* !NEED_LAPIC */
|
||||
printk_info("done.\n");
|
||||
post_code(0x9b);
|
||||
}
|
||||
|
|
@ -0,0 +1,316 @@
|
|||
#include <cpu/x86/lapic.h>
|
||||
#include <delay.h>
|
||||
#include <string.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/hlt.h>
|
||||
#include <device/device.h>
|
||||
#include <device/path.h>
|
||||
#include <smp/atomic.h>
|
||||
#include <smp/spinlock.h>
|
||||
#include <cpu/cpu.h>
|
||||
|
||||
|
||||
#if CONFIG_SMP == 1
|
||||
/* This is a lot more paranoid now, since Linux can NOT handle
|
||||
* being told there is a CPU when none exists. So any errors
|
||||
* will return 0, meaning no CPU.
|
||||
*
|
||||
* We actually handling that case by noting which cpus startup
|
||||
* and not telling anyone about the ones that dont.
|
||||
*/
|
||||
static int lapic_start_cpu(unsigned long apicid)
|
||||
{
|
||||
int timeout;
|
||||
unsigned long send_status, accept_status, start_eip;
|
||||
int j, num_starts, maxlvt;
|
||||
extern char _secondary_start[];
|
||||
|
||||
/*
|
||||
* Starting actual IPI sequence...
|
||||
*/
|
||||
|
||||
printk_spew("Asserting INIT.\n");
|
||||
|
||||
/*
|
||||
* Turn INIT on target chip
|
||||
*/
|
||||
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
|
||||
|
||||
/*
|
||||
* Send IPI
|
||||
*/
|
||||
|
||||
lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
|
||||
| LAPIC_DM_INIT);
|
||||
|
||||
printk_spew("Waiting for send to finish...\n");
|
||||
timeout = 0;
|
||||
do {
|
||||
printk_spew("+");
|
||||
udelay(100);
|
||||
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
|
||||
} while (send_status && (timeout++ < 1000));
|
||||
if (timeout >= 1000) {
|
||||
printk_err("CPU %d: First apic write timed out. Disabling\n",
|
||||
apicid);
|
||||
// too bad.
|
||||
printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
|
||||
if (lapic_read(LAPIC_ESR)) {
|
||||
printk_err("Try to reset ESR\n");
|
||||
lapic_write_around(LAPIC_ESR, 0);
|
||||
printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
mdelay(10);
|
||||
|
||||
printk_spew("Deasserting INIT.\n");
|
||||
|
||||
/* Target chip */
|
||||
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
|
||||
|
||||
/* Send IPI */
|
||||
lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
|
||||
|
||||
printk_spew("Waiting for send to finish...\n");
|
||||
timeout = 0;
|
||||
do {
|
||||
printk_spew("+");
|
||||
udelay(100);
|
||||
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
|
||||
} while (send_status && (timeout++ < 1000));
|
||||
if (timeout >= 1000) {
|
||||
printk_err("CPU %d: Second apic write timed out. Disabling\n",
|
||||
apicid);
|
||||
// too bad.
|
||||
return 0;
|
||||
}
|
||||
|
||||
start_eip = (unsigned long)_secondary_start;
|
||||
printk_spew("start_eip=0x%08lx\n", start_eip);
|
||||
|
||||
num_starts = 2;
|
||||
|
||||
/*
|
||||
* Run STARTUP IPI loop.
|
||||
*/
|
||||
printk_spew("#startup loops: %d.\n", num_starts);
|
||||
|
||||
maxlvt = 4;
|
||||
|
||||
for (j = 1; j <= num_starts; j++) {
|
||||
printk_spew("Sending STARTUP #%d to %u.\n", j, apicid);
|
||||
lapic_read_around(LAPIC_SPIV);
|
||||
lapic_write(LAPIC_ESR, 0);
|
||||
lapic_read(LAPIC_ESR);
|
||||
printk_spew("After apic_write.\n");
|
||||
|
||||
/*
|
||||
* STARTUP IPI
|
||||
*/
|
||||
|
||||
/* Target chip */
|
||||
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
|
||||
|
||||
/* Boot on the stack */
|
||||
/* Kick the second */
|
||||
lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP
|
||||
| (start_eip >> 12));
|
||||
|
||||
/*
|
||||
* Give the other CPU some time to accept the IPI.
|
||||
*/
|
||||
udelay(300);
|
||||
|
||||
printk_spew("Startup point 1.\n");
|
||||
|
||||
printk_spew("Waiting for send to finish...\n");
|
||||
timeout = 0;
|
||||
do {
|
||||
printk_spew("+");
|
||||
udelay(100);
|
||||
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
|
||||
} while (send_status && (timeout++ < 1000));
|
||||
|
||||
/*
|
||||
* Give the other CPU some time to accept the IPI.
|
||||
*/
|
||||
udelay(200);
|
||||
/*
|
||||
* Due to the Pentium erratum 3AP.
|
||||
*/
|
||||
if (maxlvt > 3) {
|
||||
lapic_read_around(LAPIC_SPIV);
|
||||
lapic_write(LAPIC_ESR, 0);
|
||||
}
|
||||
accept_status = (lapic_read(LAPIC_ESR) & 0xEF);
|
||||
if (send_status || accept_status)
|
||||
break;
|
||||
}
|
||||
printk_spew("After Startup.\n");
|
||||
if (send_status)
|
||||
printk_warning("APIC never delivered???\n");
|
||||
if (accept_status)
|
||||
printk_warning("APIC delivery error (%lx).\n", accept_status);
|
||||
if (send_status || accept_status)
|
||||
return 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Number of cpus that are currently running in linuxbios */
|
||||
static atomic_t active_cpus = ATOMIC_INIT(1);
|
||||
|
||||
/* start_cpu_lock covers last_cpu_index and secondary_stack.
|
||||
* Only starting one cpu at a time let's me remove the logic
|
||||
* for select the stack from assembly language.
|
||||
*
|
||||
* In addition communicating by variables to the cpu I
|
||||
* am starting allows me to veryify it has started before
|
||||
* start_cpu returns.
|
||||
*/
|
||||
|
||||
static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED;
|
||||
static unsigned last_cpu_index = 0;
|
||||
volatile unsigned long secondary_stack;
|
||||
|
||||
int start_cpu(device_t cpu)
|
||||
{
|
||||
extern unsigned char _estack[];
|
||||
struct cpu_info *info;
|
||||
unsigned long stack_end;
|
||||
unsigned long apicid;
|
||||
unsigned long index;
|
||||
unsigned long count;
|
||||
int result;
|
||||
|
||||
spin_lock(&start_cpu_lock);
|
||||
|
||||
/* Get the cpu's apicid */
|
||||
apicid = cpu->path.u.apic.apic_id;
|
||||
|
||||
/* Get an index for the new processor */
|
||||
index = ++last_cpu_index;
|
||||
|
||||
/* Find end of the new processors stack */
|
||||
stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
|
||||
|
||||
/* Record the index and which cpu structure we are using */
|
||||
info = (struct cpu_info *)stack_end;
|
||||
info->index = index;
|
||||
info->cpu = cpu;
|
||||
|
||||
/* Advertise the new stack to start_cpu */
|
||||
secondary_stack = stack_end;
|
||||
|
||||
/* Until the cpu starts up report the cpu is not enabled */
|
||||
cpu->enabled = 0;
|
||||
cpu->initialized = 0;
|
||||
|
||||
/* Start the cpu */
|
||||
result = lapic_start_cpu(apicid);
|
||||
|
||||
if (result) {
|
||||
result = 0;
|
||||
/* Wait 1s or until the new the new cpu calls in */
|
||||
for(count = 0; count < 100000 ; count++) {
|
||||
if (secondary_stack == 0) {
|
||||
result = 1;
|
||||
break;
|
||||
}
|
||||
udelay(10);
|
||||
}
|
||||
}
|
||||
secondary_stack = 0;
|
||||
spin_unlock(&start_cpu_lock);
|
||||
return result;
|
||||
}
|
||||
|
||||
/* C entry point of secondary cpus */
|
||||
void secondary_cpu_init(void)
|
||||
{
|
||||
atomic_inc(&active_cpus);
|
||||
cpu_initialize();
|
||||
atomic_dec(&active_cpus);
|
||||
stop_this_cpu();
|
||||
}
|
||||
|
||||
static void initialize_other_cpus(device_t root)
|
||||
{
|
||||
int old_active_count, active_count;
|
||||
device_t cpu;
|
||||
/* Loop through the cpus once getting them started */
|
||||
for(cpu = root->link[1].children; cpu ; cpu = cpu->sibling) {
|
||||
if (cpu->path.type != DEVICE_PATH_APIC) {
|
||||
continue;
|
||||
}
|
||||
if (!cpu->enabled) {
|
||||
continue;
|
||||
}
|
||||
if (cpu->initialized) {
|
||||
continue;
|
||||
}
|
||||
if (!start_cpu(cpu)) {
|
||||
/* Record the error in cpu? */
|
||||
printk_err("CPU %u would not start!\n",
|
||||
cpu->path.u.apic.apic_id);
|
||||
}
|
||||
}
|
||||
|
||||
/* Now loop until the other cpus have finished initializing */
|
||||
old_active_count = 1;
|
||||
active_count = atomic_read(&active_cpus);
|
||||
while(active_count > 1) {
|
||||
if (active_count != old_active_count) {
|
||||
printk_info("Waiting for %d CPUS to stop\n", active_count);
|
||||
old_active_count = active_count;
|
||||
}
|
||||
udelay(10);
|
||||
active_count = atomic_read(&active_cpus);
|
||||
}
|
||||
for(cpu = root->link[1].children; cpu; cpu = cpu->sibling) {
|
||||
if (cpu->path.type != DEVICE_PATH_APIC) {
|
||||
continue;
|
||||
}
|
||||
if (!cpu->initialized) {
|
||||
printk_err("CPU %u did not initialize!\n",
|
||||
cpu->path.u.apic.apic_id);
|
||||
#warning "FIXME do I need a mainboard_cpu_fixup function?"
|
||||
}
|
||||
}
|
||||
printk_debug("All AP CPUs stopped\n");
|
||||
}
|
||||
|
||||
#else /* CONFIG_SMP */
|
||||
#define initialize_other_cpus(root) do {} while(0)
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
void initialize_cpus(device_t root)
|
||||
{
|
||||
struct device_path cpu_path;
|
||||
struct cpu_info *info;
|
||||
|
||||
/* Find the info struct for this cpu */
|
||||
info = cpu_info();
|
||||
|
||||
#if NEED_LAPIC == 1
|
||||
/* Ensure the local apic is enabled */
|
||||
enable_lapic();
|
||||
|
||||
/* Get the device path of the boot cpu */
|
||||
cpu_path.type = DEVICE_PATH_APIC;
|
||||
cpu_path.u.apic.apic_id = lapicid();
|
||||
#else
|
||||
/* Get the device path of the boot cpu */
|
||||
cpu_path.type = DEVICE_PATH_BOOT_CPU;
|
||||
#endif
|
||||
|
||||
/* Find the device structure for the boot cpu */
|
||||
info->cpu = alloc_find_dev(&root->link[1], &cpu_path);
|
||||
|
||||
/* Initialize the bootstrap processor */
|
||||
cpu_initialize();
|
||||
|
||||
/* Now initialize the rest of the cpus */
|
||||
initialize_other_cpus(root);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
#include <arch/asm.h>
|
||||
#include <arch/intel.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/lapic_def.h>
|
||||
.text
|
||||
.globl _secondary_start
|
||||
.balign 4096
|
||||
_secondary_start:
|
||||
.code16
|
||||
cli
|
||||
xorl %eax, %eax
|
||||
movl %eax, %cr3 /* Invalidate TLB*/
|
||||
|
||||
/* On hyper threaded cpus, invalidating the cache here is
|
||||
* very very bad. Don't.
|
||||
*/
|
||||
|
||||
/* setup the data segment */
|
||||
movw %cs, %ax
|
||||
movw %ax, %ds
|
||||
|
||||
data32 lgdt gdtaddr - _secondary_start
|
||||
|
||||
movl %cr0, %eax
|
||||
andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
|
||||
orl $0x60000001, %eax /* CD, NW, PE = 1 */
|
||||
movl %eax, %cr0
|
||||
|
||||
ljmpl $0x10, $1f
|
||||
1:
|
||||
.code32
|
||||
movw $0x18, %ax
|
||||
movw %ax, %ds
|
||||
movw %ax, %es
|
||||
movw %ax, %ss
|
||||
movw %ax, %fs
|
||||
movw %ax, %gs
|
||||
|
||||
/* Set the stack pointer, and flag that we are done */
|
||||
xorl %eax, %eax
|
||||
movl secondary_stack, %esp
|
||||
movl %eax, secondary_stack
|
||||
|
||||
call secondary_cpu_init
|
||||
1: hlt
|
||||
jmp 1b
|
||||
|
||||
gdtaddr:
|
||||
.word gdt_limit /* the table limit */
|
||||
.long gdt /* we know the offset */
|
||||
|
||||
|
||||
.code32
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
/* Clear out an mmx state */
|
||||
emms
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
/* BIST in %eax */
|
||||
|
||||
/*
|
||||
* Enabling mmx registers is a noop
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
object mtrr.o
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
#ifndef EARLYMTRR_C
|
||||
#define EARLYMTRR_C
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
|
||||
/* Validate XIP_ROM_SIZE and XIP_ROM_BASE */
|
||||
#if defined(XIP_ROM_SIZE) && !defined(XIP_ROM_BASE)
|
||||
#error "XIP_ROM_SIZE without XIP_ROM_BASE"
|
||||
#endif
|
||||
#if defined(XIP_ROM_BASE) && !defined(XIP_ROM_SIZE)
|
||||
#error "XIP_ROM_BASE without XIP_ROM_SIZE"
|
||||
#endif
|
||||
#if !defined(CONFIG_LB_MEM_TOPK)
|
||||
#error "CONFIG_LB_MEM_TOPK not defined"
|
||||
#endif
|
||||
|
||||
#if defined(XIP_ROM_SIZE) && ((XIP_ROM_SIZE & (XIP_ROM_SIZE -1)) != 0)
|
||||
#error "XIP_ROM_SIZE is not a power of 2"
|
||||
#endif
|
||||
#if defined(XIP_ROM_SIZE) && ((XIP_ROM_BASE % XIP_ROM_SIZE) != 0)
|
||||
#error "XIP_ROM_BASE is not a multiple of XIP_ROM_SIZE"
|
||||
#endif
|
||||
|
||||
#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
|
||||
# error "CONFIG_LB_MEM_TOPK must be a power of 2"
|
||||
#endif
|
||||
|
||||
static void disable_var_mtrr(unsigned reg)
|
||||
{
|
||||
/* The invalid bit is kept in the mask so we simply
|
||||
* clear the relevent mask register to disable a
|
||||
* range.
|
||||
*/
|
||||
msr_t zero;
|
||||
zero.lo = zero.hi = 0;
|
||||
wrmsr(MTRRphysMask_MSR(reg), zero);
|
||||
}
|
||||
|
||||
static void set_var_mtrr(
|
||||
unsigned reg, unsigned base, unsigned size, unsigned type)
|
||||
|
||||
{
|
||||
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
|
||||
msr_t basem, maskm;
|
||||
basem.lo = base | type;
|
||||
basem.hi = 0;
|
||||
wrmsr(MTRRphysBase_MSR(reg), basem);
|
||||
maskm.lo = ~(size - 1) | 0x800;
|
||||
maskm.hi = 0x0f;
|
||||
wrmsr(MTRRphysMask_MSR(reg), maskm);
|
||||
}
|
||||
|
||||
static void cache_lbmem(int type)
|
||||
{
|
||||
/* Enable caching for 0 - 1MB using variable mtrr */
|
||||
disable_cache();
|
||||
set_var_mtrr(0, 0x00000000, CONFIG_LB_MEM_TOPK << 10, type);
|
||||
enable_cache();
|
||||
}
|
||||
|
||||
|
||||
/* the fixed and variable MTTRs are power-up with random values,
|
||||
* clear them to MTRR_TYPE_UNCACHEABLE for safty.
|
||||
*/
|
||||
static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
|
||||
{
|
||||
/* Precondition:
|
||||
* The cache is not enabled in cr0 nor in MTRRdefType_MSR
|
||||
* entry32.inc ensures the cache is not enabled in cr0
|
||||
*/
|
||||
msr_t msr;
|
||||
const unsigned long *msr_addr;
|
||||
unsigned long cr0;
|
||||
|
||||
print_spew("Clearing mtrr\r\n");
|
||||
|
||||
/* Inialize all of the relevant msrs to 0 */
|
||||
msr.lo = 0;
|
||||
msr.hi = 0;
|
||||
unsigned long msr_nr;
|
||||
for(msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) {
|
||||
wrmsr(msr_nr, msr);
|
||||
}
|
||||
|
||||
#if defined(XIP_ROM_SIZE)
|
||||
/* enable write through caching so we can do execute in place
|
||||
* on the flash rom.
|
||||
*/
|
||||
set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
|
||||
#endif
|
||||
|
||||
/* Set the default memory type and enable fixed and variable MTRRs
|
||||
*/
|
||||
/* Enable Variable MTRRs */
|
||||
msr.hi = 0x00000000;
|
||||
msr.lo = 0x00000800;
|
||||
wrmsr(MTRRdefType_MSR, msr);
|
||||
|
||||
}
|
||||
|
||||
static void early_mtrr_init(void)
|
||||
{
|
||||
static const unsigned long mtrr_msrs[] = {
|
||||
/* fixed mtrr */
|
||||
0x250, 0x258, 0x259,
|
||||
0x268, 0x269, 0x26A,
|
||||
0x26B, 0x26C, 0x26D,
|
||||
0x26E, 0x26F,
|
||||
/* var mtrr */
|
||||
0x200, 0x201, 0x202, 0x203,
|
||||
0x204, 0x205, 0x206, 0x207,
|
||||
0x208, 0x209, 0x20A, 0x20B,
|
||||
0x20C, 0x20D, 0x20E, 0x20F,
|
||||
/* NULL end of table */
|
||||
0
|
||||
};
|
||||
disable_cache();
|
||||
do_early_mtrr_init(mtrr_msrs);
|
||||
enable_cache();
|
||||
}
|
||||
|
||||
#endif /* EARLYMTRR_C */
|
||||
|
|
@ -0,0 +1,378 @@
|
|||
/*
|
||||
* intel_mtrr.c: setting MTRR to decent values for cache initialization on P6
|
||||
*
|
||||
* Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel
|
||||
*
|
||||
* Copyright 2000 Silicon Integrated System Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*
|
||||
* Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
|
||||
#define arraysize(x) (sizeof(x)/sizeof((x)[0]))
|
||||
|
||||
#warning "FIXME I do not properly handle address more than 36 physical address bits"
|
||||
#ifdef k8
|
||||
# define ADDRESS_BITS 40
|
||||
#else
|
||||
# define ADDRESS_BITS 36
|
||||
#endif
|
||||
#define ADDRESS_BITS_HIGH (ADDRESS_BITS - 32)
|
||||
#define ADDRESS_MASK_HIGH ((1u << ADDRESS_BITS_HIGH) - 1)
|
||||
|
||||
static unsigned int mtrr_msr[] = {
|
||||
MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
|
||||
MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
|
||||
MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
|
||||
};
|
||||
|
||||
|
||||
static void enable_fixed_mtrr(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
msr = rdmsr(MTRRdefType_MSR);
|
||||
msr.lo |= 0xc00;
|
||||
wrmsr(MTRRdefType_MSR, msr);
|
||||
}
|
||||
|
||||
static void enable_var_mtrr(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
msr = rdmsr(MTRRdefType_MSR);
|
||||
msr.lo |= 0x800;
|
||||
wrmsr(MTRRdefType_MSR, msr);
|
||||
}
|
||||
|
||||
/* setting variable mtrr, comes from linux kernel source */
|
||||
static void set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type)
|
||||
{
|
||||
msr_t base, mask;
|
||||
|
||||
base.hi = basek >> 22;
|
||||
base.lo = basek << 10;
|
||||
|
||||
//printk_debug("ADDRESS_MASK_HIGH=%#x\n", ADDRESS_MASK_HIGH);
|
||||
|
||||
if (sizek < 4*1024*1024) {
|
||||
mask.hi = ADDRESS_MASK_HIGH;
|
||||
mask.lo = ~((sizek << 10) -1);
|
||||
}
|
||||
else {
|
||||
mask.hi = ADDRESS_MASK_HIGH & (~((sizek >> 22) -1));
|
||||
mask.lo = 0;
|
||||
}
|
||||
|
||||
if (reg >= 8)
|
||||
return;
|
||||
|
||||
// it is recommended that we disable and enable cache when we
|
||||
// do this.
|
||||
disable_cache();
|
||||
if (sizek == 0) {
|
||||
msr_t zero;
|
||||
zero.lo = zero.hi = 0;
|
||||
/* The invalid bit is kept in the mask, so we simply clear the
|
||||
relevant mask register to disable a range. */
|
||||
wrmsr (MTRRphysMask_MSR(reg), zero);
|
||||
} else {
|
||||
/* Bit 32-35 of MTRRphysMask should be set to 1 */
|
||||
base.lo |= type;
|
||||
mask.lo |= 0x800;
|
||||
wrmsr (MTRRphysBase_MSR(reg), base);
|
||||
wrmsr (MTRRphysMask_MSR(reg), mask);
|
||||
}
|
||||
enable_cache();
|
||||
}
|
||||
|
||||
/* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
|
||||
static inline unsigned int fms(unsigned int x)
|
||||
{
|
||||
int r;
|
||||
|
||||
__asm__("bsrl %1,%0\n\t"
|
||||
"jnz 1f\n\t"
|
||||
"movl $0,%0\n"
|
||||
"1:" : "=r" (r) : "g" (x));
|
||||
return r;
|
||||
}
|
||||
|
||||
/* fms: find least sigificant bit set */
|
||||
static inline unsigned int fls(unsigned int x)
|
||||
{
|
||||
int r;
|
||||
|
||||
__asm__("bsfl %1,%0\n\t"
|
||||
"jnz 1f\n\t"
|
||||
"movl $32,%0\n"
|
||||
"1:" : "=r" (r) : "g" (x));
|
||||
return r;
|
||||
}
|
||||
|
||||
/* setting up variable and fixed mtrr
|
||||
*
|
||||
* From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement:
|
||||
* 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum).
|
||||
* 2. The base address must be 2^N aligned, where the N here is equal to the N in previous
|
||||
* requirement. So a 8K range must be 8K aligned not 4K aligned.
|
||||
*
|
||||
* These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]).
|
||||
* For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]).
|
||||
* A 124MB (128MB - 4MB SMA) example:
|
||||
* ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB).
|
||||
* But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions.
|
||||
*
|
||||
* In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible,
|
||||
* If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula
|
||||
* whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used.
|
||||
* The same 124MB example:
|
||||
* ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB)
|
||||
* or a 156MB (128MB + 32MB - 4MB SMA) example:
|
||||
* ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
|
||||
*/
|
||||
/* 2 MTRRS are reserved for the operating system */
|
||||
#if 0
|
||||
#define BIOS_MTRRS 6
|
||||
#define OS_MTRRS 2
|
||||
#else
|
||||
#define BIOS_MTRRS 8
|
||||
#define OS_MTRRS 0
|
||||
#endif
|
||||
#define MTRRS (BIOS_MTRRS + OS_MTRRS)
|
||||
|
||||
|
||||
static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
|
||||
msr_t msr;
|
||||
msr.lo = msr.hi = 0; /* Shut up gcc */
|
||||
for(i = first; i < last; i++) {
|
||||
/* When I switch to a new msr read it in */
|
||||
if (fixed_msr != i >> 3) {
|
||||
/* But first write out the old msr */
|
||||
if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
|
||||
disable_cache();
|
||||
wrmsr(mtrr_msr[fixed_msr], msr);
|
||||
enable_cache();
|
||||
}
|
||||
fixed_msr = i>>3;
|
||||
msr = rdmsr(mtrr_msr[fixed_msr]);
|
||||
}
|
||||
if ((i & 7) < 4) {
|
||||
msr.lo &= ~(0xff << ((i&3)*8));
|
||||
msr.lo |= type << ((i&3)*8);
|
||||
} else {
|
||||
msr.hi &= ~(0xff << ((i&3)*8));
|
||||
msr.hi |= type << ((i&3)*8);
|
||||
}
|
||||
}
|
||||
/* Write out the final msr */
|
||||
if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
|
||||
disable_cache();
|
||||
wrmsr(mtrr_msr[fixed_msr], msr);
|
||||
enable_cache();
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned fixed_mtrr_index(unsigned long addrk)
|
||||
{
|
||||
unsigned index;
|
||||
index = (addrk - 0) >> 6;
|
||||
if (index >= 8) {
|
||||
index = ((addrk - 8*64) >> 4) + 8;
|
||||
}
|
||||
if (index >= 24) {
|
||||
index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
|
||||
}
|
||||
if (index > NUM_FIXED_RANGES) {
|
||||
index = NUM_FIXED_RANGES;
|
||||
}
|
||||
return index;
|
||||
}
|
||||
|
||||
static unsigned int range_to_mtrr(unsigned int reg,
|
||||
unsigned long range_startk, unsigned long range_sizek,
|
||||
unsigned long next_range_startk)
|
||||
{
|
||||
if (!range_sizek || (reg >= BIOS_MTRRS)) {
|
||||
return reg;
|
||||
}
|
||||
while(range_sizek) {
|
||||
unsigned long max_align, align;
|
||||
unsigned long sizek;
|
||||
/* Compute the maximum size I can make a range */
|
||||
max_align = fls(range_startk);
|
||||
align = fms(range_sizek);
|
||||
if (align > max_align) {
|
||||
align = max_align;
|
||||
}
|
||||
sizek = 1 << align;
|
||||
printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type WB\n",
|
||||
reg, range_startk >>10, sizek >> 10);
|
||||
set_var_mtrr(reg++, range_startk, sizek, MTRR_TYPE_WRBACK);
|
||||
range_startk += sizek;
|
||||
range_sizek -= sizek;
|
||||
if (reg >= BIOS_MTRRS)
|
||||
break;
|
||||
}
|
||||
return reg;
|
||||
}
|
||||
|
||||
static unsigned long resk(uint64_t value)
|
||||
{
|
||||
unsigned long resultk;
|
||||
if (value < (1ULL << 42)) {
|
||||
resultk = value >> 10;
|
||||
}
|
||||
else {
|
||||
resultk = 0xffffffff;
|
||||
}
|
||||
return resultk;
|
||||
}
|
||||
|
||||
void x86_setup_mtrrs(void)
|
||||
{
|
||||
/* Try this the simple way of incrementally adding together
|
||||
* mtrrs. If this doesn't work out we can get smart again
|
||||
* and clear out the mtrrs.
|
||||
*/
|
||||
struct device *dev;
|
||||
unsigned long range_startk, range_sizek;
|
||||
unsigned int reg;
|
||||
|
||||
printk_debug("\n");
|
||||
/* Initialized the fixed_mtrrs to uncached */
|
||||
printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
|
||||
0, NUM_FIXED_RANGES);
|
||||
set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
|
||||
|
||||
/* Now see which of the fixed mtrrs cover ram.
|
||||
*/
|
||||
for(dev = all_devices; dev; dev = dev->next) {
|
||||
struct resource *res, *last;
|
||||
last = &dev->resource[dev->resources];
|
||||
for(res = &dev->resource[0]; res < last; res++) {
|
||||
unsigned int start_mtrr;
|
||||
unsigned int last_mtrr;
|
||||
if (!(res->flags & IORESOURCE_MEM) ||
|
||||
!(res->flags & IORESOURCE_CACHEABLE))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
start_mtrr = fixed_mtrr_index(resk(res->base));
|
||||
last_mtrr = fixed_mtrr_index(resk((res->base + res->size)));
|
||||
if (start_mtrr >= NUM_FIXED_RANGES) {
|
||||
break;
|
||||
}
|
||||
printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
|
||||
start_mtrr, last_mtrr);
|
||||
set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
|
||||
}
|
||||
}
|
||||
printk_debug("DONE fixed MTRRs\n");
|
||||
/* Cache as many memory areas as possible */
|
||||
/* FIXME is there an algorithm for computing the optimal set of mtrrs?
|
||||
* In some cases it is definitely possible to do better.
|
||||
*/
|
||||
range_startk = 0;
|
||||
range_sizek = 0;
|
||||
reg = 0;
|
||||
for(dev = all_devices; dev; dev = dev->next) {
|
||||
struct resource *res, *last;
|
||||
last = &dev->resource[dev->resources];
|
||||
for(res = &dev->resource[0]; res < last; res++) {
|
||||
unsigned long basek, sizek;
|
||||
if (!(res->flags & IORESOURCE_MEM) ||
|
||||
!(res->flags & IORESOURCE_CACHEABLE)) {
|
||||
continue;
|
||||
}
|
||||
basek = resk(res->base);
|
||||
sizek = resk(res->size);
|
||||
/* See if I can merge with the last range
|
||||
* Either I am below 1M and the fixed mtrrs handle it, or
|
||||
* the ranges touch.
|
||||
*/
|
||||
if ((basek <= 1024) || (range_startk + range_sizek == basek)) {
|
||||
unsigned long endk = basek + sizek;
|
||||
range_sizek = endk - range_startk;
|
||||
continue;
|
||||
}
|
||||
/* Write the range mtrrs */
|
||||
if (range_sizek != 0) {
|
||||
reg = range_to_mtrr(reg, range_startk, range_sizek, basek);
|
||||
range_startk = 0;
|
||||
range_sizek = 0;
|
||||
if (reg >= BIOS_MTRRS)
|
||||
goto last_msr;
|
||||
}
|
||||
/* Allocate an msr */
|
||||
range_startk = basek;
|
||||
range_sizek = sizek;
|
||||
}
|
||||
}
|
||||
last_msr:
|
||||
/* Write the last range */
|
||||
reg = range_to_mtrr(reg, range_startk, range_sizek, 0);
|
||||
printk_debug("DONE variable MTRRs\n");
|
||||
printk_debug("Clear out the extra MTRR's\n");
|
||||
/* Clear out the extra MTRR's */
|
||||
while(reg < MTRRS) {
|
||||
set_var_mtrr(reg++, 0, 0, 0);
|
||||
}
|
||||
/* enable fixed MTRR */
|
||||
printk_spew("call enable_fixed_mtrr()\n");
|
||||
enable_fixed_mtrr();
|
||||
printk_spew("call enable_var_mtrr()\n");
|
||||
enable_var_mtrr();
|
||||
printk_spew("Leave %s\n", __FUNCTION__);
|
||||
post_code(0x6A);
|
||||
}
|
||||
|
||||
int x86_mtrr_check(void)
|
||||
{
|
||||
/* Only Pentium Pro and later have MTRR */
|
||||
msr_t msr;
|
||||
printk_debug("\nMTRR check\n");
|
||||
|
||||
msr = rdmsr(0x2ff);
|
||||
msr.lo >>= 10;
|
||||
|
||||
printk_debug("Fixed MTRRs : ");
|
||||
if (msr.lo & 0x01)
|
||||
printk_debug("Enabled\n");
|
||||
else
|
||||
printk_debug("Disabled\n");
|
||||
|
||||
printk_debug("Variable MTRRs: ");
|
||||
if (msr.lo & 0x02)
|
||||
printk_debug("Enabled\n");
|
||||
else
|
||||
printk_debug("Disabled\n");
|
||||
|
||||
printk_debug("\n");
|
||||
|
||||
post_code(0x93);
|
||||
return ((int) msr.lo);
|
||||
}
|
||||
|
|
@ -0,0 +1 @@
|
|||
object pgtbl.o
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
#include <console/console.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/pae.h>
|
||||
#include <string.h>
|
||||
|
||||
static void paging_off(void)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
/* Disable paging */
|
||||
"movl %%cr0, %%eax\n\t"
|
||||
"andl $0x7FFFFFFF, %%eax\n\t"
|
||||
"movl %%eax, %%cr0\n\t"
|
||||
/* Disable pae */
|
||||
"movl %%cr4, %%eax\n\t"
|
||||
"andl $0xFFFFFFDF, %%eax\n\t"
|
||||
:
|
||||
:
|
||||
: "eax"
|
||||
);
|
||||
}
|
||||
|
||||
static void paging_on(void *pdp)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
/* Load the page table address */
|
||||
"movl %0, %%cr3\n\t"
|
||||
/* Enable pae */
|
||||
"movl %%cr4, %%eax\n\t"
|
||||
"orl $0x00000020, %%eax\n\t"
|
||||
"movl %%eax, %%cr4\n\t"
|
||||
/* Enable paging */
|
||||
"movl %%cr0, %%eax\n\t"
|
||||
"orl $0x80000000, %%eax\n\t"
|
||||
"movl %%eax, %%cr0\n\t"
|
||||
:
|
||||
: "r" (pdp)
|
||||
: "eax"
|
||||
);
|
||||
}
|
||||
|
||||
void *map_2M_page(unsigned long page)
|
||||
{
|
||||
struct pde {
|
||||
uint32_t addr_lo;
|
||||
uint32_t addr_hi;
|
||||
} __attribute__ ((packed));
|
||||
struct pg_table {
|
||||
struct pde pd[2048];
|
||||
struct pde pdp[512];
|
||||
} __attribute__ ((packed));
|
||||
static struct pg_table pgtbl[CONFIG_MAX_CPUS] __attribute__ ((aligned(4096)));
|
||||
static unsigned long mapped_window[CONFIG_MAX_CPUS];
|
||||
unsigned long index;
|
||||
unsigned long window;
|
||||
void *result;
|
||||
int i;
|
||||
index = cpu_index();
|
||||
if ((index < 0) || (index >= CONFIG_MAX_CPUS)) {
|
||||
return MAPPING_ERROR;
|
||||
}
|
||||
window = page >> 10;
|
||||
if (window != mapped_window[index]) {
|
||||
paging_off();
|
||||
if (window > 1) {
|
||||
struct pde *pd, *pdp;
|
||||
/* Point the page directory pointers at the page directories */
|
||||
memset(&pgtbl[index].pdp, 0, sizeof(pgtbl[index].pdp));
|
||||
pd = pgtbl[index].pd;
|
||||
pdp = pgtbl[index].pdp;
|
||||
pdp[0].addr_lo = ((uint32_t)&pd[512*0])|1;
|
||||
pdp[1].addr_lo = ((uint32_t)&pd[512*1])|1;
|
||||
pdp[2].addr_lo = ((uint32_t)&pd[512*2])|1;
|
||||
pdp[3].addr_lo = ((uint32_t)&pd[512*3])|1;
|
||||
/* The first half of the page table is identity mapped */
|
||||
for(i = 0; i < 1024; i++) {
|
||||
pd[i].addr_lo = ((i & 0x3ff) << 21)| 0xE3;
|
||||
pd[i].addr_hi = 0;
|
||||
}
|
||||
/* The second half of the page table holds the mapped page */
|
||||
for(i = 1024; i < 2048; i++) {
|
||||
pd[i].addr_lo = ((window & 1) << 31) | ((i & 0x3ff) << 21) | 0xE3;
|
||||
pd[i].addr_hi = (window >> 1);
|
||||
}
|
||||
paging_on(pdp);
|
||||
}
|
||||
mapped_window[index] = window;
|
||||
}
|
||||
if (window == 0) {
|
||||
result = (void *)(page << 21);
|
||||
} else {
|
||||
result = (void *)(0x80000000 | ((page & 0x3ff) << 21));
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* Put the processor back into a reset state
|
||||
* with respect to the xmm registers.
|
||||
*/
|
||||
|
||||
xorps %xmm0, %xmm0
|
||||
xorps %xmm1, %xmm1
|
||||
xorps %xmm2, %xmm2
|
||||
xorps %xmm3, %xmm3
|
||||
xorps %xmm4, %xmm4
|
||||
xorps %xmm5, %xmm5
|
||||
xorps %xmm6, %xmm6
|
||||
xorps %xmm7, %xmm7
|
||||
|
||||
/* Disable sse instructions */
|
||||
movl %cr4, %eax
|
||||
andl $~(3<<9), %eax
|
||||
movl %eax, %cr4
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/* preserve BIST in %eax */
|
||||
movl %eax, %ebp
|
||||
|
||||
/*
|
||||
* Enable the use of the xmm registers
|
||||
*/
|
||||
|
||||
/* Enable sse instructions */
|
||||
movl %cr4, %eax
|
||||
orl $(1<<9), %eax
|
||||
movl %eax, %cr4
|
||||
|
||||
movl %ebp, %eax
|
||||
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
|
||||
if CONFIG_UDELAY_TSC object delay_tsc.o end
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/tsc.h>
|
||||
#include <smp/spinlock.h>
|
||||
#include <delay.h>
|
||||
|
||||
static unsigned long clocks_per_usec;
|
||||
|
||||
#if (CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 == 1)
|
||||
#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */
|
||||
|
||||
/* ------ Calibrate the TSC -------
|
||||
* Too much 64-bit arithmetic here to do this cleanly in C, and for
|
||||
* accuracy's sake we want to keep the overhead on the CTC speaker (channel 2)
|
||||
* output busy loop as low as possible. We avoid reading the CTC registers
|
||||
* directly because of the awkward 8-bit access mechanism of the 82C54
|
||||
* device.
|
||||
*/
|
||||
|
||||
#define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */
|
||||
#define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */
|
||||
|
||||
static unsigned long long calibrate_tsc(void)
|
||||
{
|
||||
/* Set the Gate high, disable speaker */
|
||||
outb((inb(0x61) & ~0x02) | 0x01, 0x61);
|
||||
|
||||
/*
|
||||
* Now let's take care of CTC channel 2
|
||||
*
|
||||
* Set the Gate high, program CTC channel 2 for mode 0,
|
||||
* (interrupt on terminal count mode), binary count,
|
||||
* load 5 * LATCH count, (LSB and MSB) to begin countdown.
|
||||
*/
|
||||
outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
|
||||
outb(CALIBRATE_INTERVAL & 0xff, 0x42); /* LSB of count */
|
||||
outb(CALIBRATE_INTERVAL >> 8, 0x42); /* MSB of count */
|
||||
|
||||
{
|
||||
tsc_t start;
|
||||
tsc_t end;
|
||||
unsigned long count;
|
||||
|
||||
start = rdtsc();
|
||||
count = 0;
|
||||
do {
|
||||
count++;
|
||||
} while ((inb(0x61) & 0x20) == 0);
|
||||
end = rdtsc();
|
||||
|
||||
/* Error: ECTCNEVERSET */
|
||||
if (count <= 1)
|
||||
goto bad_ctc;
|
||||
|
||||
/* 64-bit subtract - gcc just messes up with long longs */
|
||||
__asm__("subl %2,%0\n\t"
|
||||
"sbbl %3,%1"
|
||||
:"=a" (end.lo), "=d" (end.hi)
|
||||
:"g" (start.lo), "g" (start.hi),
|
||||
"0" (end.lo), "1" (end.hi));
|
||||
|
||||
/* Error: ECPUTOOFAST */
|
||||
if (end.hi)
|
||||
goto bad_ctc;
|
||||
|
||||
|
||||
/* Error: ECPUTOOSLOW */
|
||||
if (end.lo <= CALIBRATE_DIVISOR)
|
||||
goto bad_ctc;
|
||||
|
||||
return (end.lo + CALIBRATE_DIVISOR -1)/CALIBRATE_DIVISOR;
|
||||
}
|
||||
|
||||
/*
|
||||
* The CTC wasn't reliable: we got a hit on the very first read,
|
||||
* or the CPU was so fast/slow that the quotient wouldn't fit in
|
||||
* 32 bits..
|
||||
*/
|
||||
bad_ctc:
|
||||
printk_err("bad_ctc\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else /* CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 */
|
||||
|
||||
/*
|
||||
* this is the "no timer2" version.
|
||||
* to calibrate tsc, we get a TSC reading, then do 1,000,000 outbs to port 0x80
|
||||
* then we read TSC again, and divide the difference by 1,000,000
|
||||
* we have found on a wide range of machines that this gives us a a
|
||||
* good microsecond value
|
||||
* to +- 10%. On a dual AMD 1.6 Ghz box, it gives us .97 microseconds, and on a
|
||||
* 267 Mhz. p5, it gives us 1.1 microseconds.
|
||||
* also, since gcc now supports long long, we use that.
|
||||
* also no unsigned long long / operator, so we play games.
|
||||
* about the only thing you can do with long longs, it seems,
|
||||
*is return them and assign them.
|
||||
* (and do asm on them, yuck)
|
||||
* so avoid all ops on long longs.
|
||||
*/
|
||||
static unsigned long long calibrate_tsc(void)
|
||||
{
|
||||
unsigned long long start, end, delta;
|
||||
unsigned long allones = (unsigned long) -1, result;
|
||||
unsigned long count;
|
||||
|
||||
start = rdtscll();
|
||||
// no udivdi3, dammit.
|
||||
// so we count to 1<< 20 and then right shift 20
|
||||
for(count = 0; count < (1<<20); count ++)
|
||||
outb(0x80, 0x80);
|
||||
end = rdtscll();
|
||||
|
||||
#if 0
|
||||
// make delta be (endhigh - starthigh) + (endlow - startlow)
|
||||
// but >> 20
|
||||
// do it this way to avoid gcc warnings.
|
||||
start = tsc_start.hi;
|
||||
start <<= 32;
|
||||
start |= start.lo;
|
||||
end = tsc_end.hi;
|
||||
end <<= 32;
|
||||
end |= tsc_end.lo;
|
||||
#endif
|
||||
delta = end - start;
|
||||
// at this point we have a delta for 1,000,000 outbs. Now rescale for one microsecond.
|
||||
delta >>= 20;
|
||||
// save this for microsecond timing.
|
||||
result = delta;
|
||||
printk_spew("end %x:%x, start %x:%x\n",
|
||||
endhigh, endlow, starthigh, startlow);
|
||||
printk_spew("32-bit delta %d\n", (unsigned long) delta);
|
||||
|
||||
printk_spew(__FUNCTION__ " 32-bit result is %d\n", result);
|
||||
return delta;
|
||||
}
|
||||
|
||||
|
||||
#endif /* CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2*/
|
||||
|
||||
void init_timer(void)
|
||||
{
|
||||
if (!clocks_per_usec) {
|
||||
clocks_per_usec = calibrate_tsc();
|
||||
printk_info("clocks_per_usec: %u\n", clocks_per_usec);
|
||||
}
|
||||
}
|
||||
|
||||
void udelay(unsigned us)
|
||||
{
|
||||
unsigned long long count;
|
||||
unsigned long long stop;
|
||||
unsigned long long clocks;
|
||||
|
||||
init_timer();
|
||||
clocks = us;
|
||||
clocks *= clocks_per_usec;
|
||||
count = rdtscll();
|
||||
stop = clocks + count;
|
||||
while(stop > count) {
|
||||
cpu_relax();
|
||||
count = rdtscll();
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue