google/gale: Remove some unwanted code
BUG=chrome-os-partner:49249 TEST=Compiles and boots BRANCH=none Original-Commit-Id: 96a125f99af3eaa8931563fa74ccef8dd997f3ca Original-Change-Id: Iebfe7429c400e7119510a51c3124d432f00af76d Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333319 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Add function to reset TPM BUG=chrome-os-partner:49249 TEST=Able to read TPM registers BRANCH=none Original-Commit-Id: 9df3e9dfe61382143394a58a3a927c05a875b377 Original-Change-Id: I38732acc4418c94b88a430ba697db4e3b145c341 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333317 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ifc8df3b7e231eef944efec3a6f973b402c11bcaf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14674 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -78,8 +78,10 @@ enum switch_state {
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static void display_pattern(int pattern)
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{
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#if IS_ENABLED(notyet)
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if (board_id() == BOARD_ID_WHIRLWIND_SP5)
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ww_ring_display_pattern(GSBI_ID_7, pattern);
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#endif
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}
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#define WIPEOUT_MODE_DELAY_MS (8 * 1000)
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@ -31,49 +31,42 @@
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static void setup_usb(void)
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{
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#if !CONFIG_BOARD_VARIANT_AP148
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gpio_tlmm_config_set(USB_ENABLE_GPIO, FUNC_SEL_GPIO,
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GPIO_PULL_UP, GPIO_10MA, GPIO_ENABLE);
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gpio_set(USB_ENABLE_GPIO, 1);
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#endif
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usb_clock_config();
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setup_usb_host1();
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}
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#define TPM_RESET_GPIO 22
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static void setup_tpm(void)
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#define TPM_RESET_GPIO 19
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static void ipq_setup_tpm(void)
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{
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if (board_id() != BOARD_ID_PROTO_0)
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return; /* Only proto0 have TPM reset connected to GPIO22 */
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gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP,
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GPIO_4MA, GPIO_ENABLE);
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/*
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* Generate a reset pulse. The spec calls for 80 us minimum, let's
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* make it twice as long. If the output was driven low originally, the
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* reset pulse will be even longer.
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*/
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#ifdef CONFIG_I2C_TPM
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gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO,
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GPIO_PULL_UP, GPIO_6MA, 1);
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gpio_set(TPM_RESET_GPIO, 0);
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udelay(160);
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udelay(100);
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gpio_set(TPM_RESET_GPIO, 1);
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}
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#define SW_RESET_GPIO 26
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static void assert_sw_reset(void)
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{
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if (board_id() == BOARD_ID_PROTO_0)
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return;
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/*
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* only proto0.2 and later care about this. We want to keep the
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* ethernet switch in reset, otherwise it comes up in default
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* (bridging) mode.
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* ----- Per the SLB 9615XQ1.2 spec -----
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*
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* 4.7.1 Reset Timing
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*
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* The TPM_ACCESS_x.tpmEstablishment bit has the correct value
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* and the TPM_ACCESS_x.tpmRegValidSts bit is typically set
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* within 8ms after RESET# is deasserted.
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*
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* The TPM is ready to receive a command after less than 30 ms.
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*
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* --------------------------------------
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*
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* I'm assuming this means "wait for 30ms"
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*
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* If we don't wait here, subsequent QUP I2C accesses
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* to the TPM either fail or timeout.
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*/
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gpio_tlmm_config_set(SW_RESET_GPIO, FUNC_SEL_GPIO,
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GPIO_PULL_UP, GPIO_4MA, GPIO_ENABLE);
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mdelay(30);
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gpio_set(SW_RESET_GPIO, 1);
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#endif /* CONFIG_I2C_TPM */
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}
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static void mainboard_init(device_t dev)
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@ -83,10 +76,8 @@ static void mainboard_init(device_t dev)
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start_tzbsp();
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/* Setup mmu and d-cache again as non secure entries. */
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setup_mmu(DRAM_INITIALIZED);
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start_rpm();
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setup_usb();
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assert_sw_reset();
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setup_tpm();
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ipq_setup_tpm();
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#if IS_ENABLED(CONFIG_CHROMEOS)
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/* Copy WIFI calibration data into CBMEM. */
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@ -99,7 +90,7 @@ static void mainboard_init(device_t dev)
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*
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* 48000 * 2 * 16 * 4 = 6144000
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*/
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audio_clock_config(6144000);
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//audio_clock_config(6144000);
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}
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static void mainboard_enable(device_t dev)
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