diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html
index d50ff4e74f..47d329515d 100644
--- a/Documentation/Intel/Board/board.html
+++ b/Documentation/Intel/Board/board.html
@@ -15,6 +15,7 @@
- Required Files
- Enable Serial Output
+ - Load the Memory Timing Data
@@ -101,6 +102,84 @@
+
+
+
+ Memory timing data is located in the flash. This data is in the format of
+ serial presence detect
+ (SPD) data.
+ Use the following steps to load the SPD data:
+
+
+ - Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the
+ display of the SPD data being passed to MemoryInit
+
+ - Create an "spd" subdirectory
+ - Create an spd/spd.c file for the SPD implementation
+
+ - Implement the mainboard_fill_spd_data routine
+
+ - Read the SPD data either from the spd.bin file or using I2C or SMBUS
+ - Fill in the pei_data structure with SPD data for each of the DIMMs
+ - Set the DIMM channel configuration
+
+
+
+
+ - Add an .spd.hex file containing the memory timing data to the spd subdirectory
+ - Create spd/Makefile.inc
+
+ - Add spd.c to romstage
+ - Add the .spd.hex file to SPD_SOURCES
+
+
+ - Edit Makefile.inc to add the spd subdirectory
+ - Edit romstage.c
+
+ - Call mainboard_fill_spd_data
+ - Add mainboard_memory_init_params to copy the SPD and DRAM
+ configuration data from the pei_data structure into the UPDs
+ for MemoryInit
+
+
+
+ - Edit devicetree.cb
+
+ - Include the UPD parameters for MemoryInit except for:
+
+ - Address of SPD data
+ - DRAM configuration set above
+
+
+
+
+ - A working FSP
+ MemoryInit
+ routine is required to complete debugging
+ - Debug the result until port 0x80 outputs
+
+ - 0x34:
+ - Just after entering
+ raminit
+
+ - 0x36:
+ - Just before displaying the
+ UPD parameters
+ for FSP MemoryInit
+
+ - 0x92: POST_FSP_MEMORY_INIT
+ - Just before calling FSP
+ MemoryInit
+
+ - 0x37:
+ - Just after returning from FSP
+ MemoryInit
+
+
+
+ - Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called
+
+
Modified: 31 January 2016
diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
index 0b0615d049..b5daac8fb5 100644
--- a/Documentation/Intel/SoC/soc.html
+++ b/Documentation/Intel/SoC/soc.html
@@ -22,6 +22,8 @@
Romstage
- Enable Serial Output"
+ - Get the Previous Sleep State
+ - Add the MemoryInit Support
@@ -328,6 +330,57 @@ Use the following steps to debug the call to TempRamInit:
+
+
+ The following steps implement the code to get the previous sleep state:
+
+
+ - Implement the fill_power_state routine which determines the previous sleep state
+ - Debug the result until port 0x80 outputs
+
+ - 0x32:
+ - Just after entering
+ romstage_common
+
+ - 0x33 - Just after calling
+ soc_pre_ram_init
+
+ - 0x34:
+ - Just after entering
+ raminit
+
+
+
+
+
+
+
+ The following steps implement the code to support the FSP MemoryInit call:
+
+
+ - Add the chip.h header file to define the UPD values which get passed
+ to MemoryInit. Skip the values containing SPD addresses and DRAM
+ configuration data which is determined by the board.
+
+ Build Note: The src/mainboard/<Vendor>/<Board>/devicetree.cb
+ file specifies the default values for these parameters. The build
+ process creates the static.c module which contains the config data
+ structure containing these values.
+
+
+ - Edit romstage/romstage.c
+
+ - Implement the romstage/romstage.c/soc_memory_init_params routine to
+ copy the values from the config structure into the UPD structure
+
+ - Implement the soc_display_memory_init_params routine to display
+ the updated UPD parameters by calling fsp_display_upd_value
+
+
+
+
+
+
Modified: 31 January 2016