src: Remove unused 'include <bootmode.h>'

Change-Id: I658023f7c3535a2cddd8e11ca8bebe20ae53ffb0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41670
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/ec/google/chromeec/ec.c

@@ -3,7 +3,6 @@
 #include <stdint.h>
 #include <string.h>
 #include <assert.h>
-#include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>

src/northbridge/intel/sandybridge/raminit.c

@@ -2,7 +2,6 @@
 
 #include <console/console.h>
 #include <commonlib/region.h>
-#include <bootmode.h>
 #include <cf9_reset.h>
 #include <string.h>
 #include <arch/cpu.h>

src/northbridge/intel/sandybridge/raminit_mrc.c

@@ -2,7 +2,6 @@
 
 #include <console/console.h>
 #include <console/usb.h>
-#include <bootmode.h>
 #include <cf9_reset.h>
 #include <string.h>
 #include <device/device.h>

src/soc/cavium/cn81xx/soc.c

@@ -4,7 +4,6 @@
  * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0.
  */
 
-#include <bootmode.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <soc/addressmap.h>

src/soc/intel/apollolake/romstage.c

@@ -4,7 +4,6 @@
 #include <device/pci_ops.h>
 #include <arch/symbols.h>
 #include <assert.h>
-#include <bootmode.h>
 #include <cbmem.h>
 #include <cf9_reset.h>
 #include <console/console.h>

src/soc/intel/broadwell/romstage/romstage.c

@@ -2,7 +2,6 @@
 
 #include <stdint.h>
 #include <arch/romstage.h>
-#include <bootmode.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>

src/soc/intel/skylake/chip.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <fsp/api.h>