mediatek/mt8183: Enable RTC eosc calibration feature to save power
When system shuts down, RTC enable eosc calibration feature to save power. Then coreboot RTC driver needs to call rtc_enable_dcxo function at every boot to switch RTC clock source to dcxo. BUG=b:128467245 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748 Signed-off-by: Ran Bi <ran.bi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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@ -91,12 +91,15 @@ int rtc_xosc_write(u16 val)
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u16 bbpu;
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rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
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udelay(200);
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if (!rtc_busy_wait())
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return 0;
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rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
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udelay(200);
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if (!rtc_busy_wait())
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return 0;
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rtc_write(RTC_OSC32CON, val);
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udelay(200);
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if (!rtc_busy_wait())
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return 0;
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rtc_read(RTC_BBPU, &bbpu);
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bbpu |= RTC_BBPU_KEY | RTC_BBPU_RELOAD;
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@ -100,18 +100,25 @@ enum {
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};
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enum {
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RTC_EMBCK_SRC_SEL = 1 << 8,
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RTC_EMBCK_SEL_MODE = 3 << 6,
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RTC_XOSC32_ENB = 1 << 5,
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RTC_REG_XOSC32_ENB = 1 << 15
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RTC_XOSCCALI_MASK = 0x1F << 0,
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RTC_XOSC32_ENB = 1U << 5,
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RTC_EMB_HW_MODE = 0U << 6,
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RTC_EMB_K_EOSC32_MODE = 1U << 6,
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RTC_EMB_SW_DCXO_MODE = 2U << 6,
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RTC_EMB_SW_EOSC32_MODE = 3U << 6,
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RTC_EMBCK_SEL_MODE_MASK = 3U << 6,
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RTC_EMBCK_SRC_SEL = 1U << 8,
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RTC_EMBCK_SEL_OPTION = 1U << 9,
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RTC_GPS_CKOUT_EN = 1U << 10,
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RTC_REG_XOSC32_ENB = 1U << 15
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};
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enum {
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RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0 << 13,
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RTC_LPD_OPT_EOSC_LPD = 1 << 13,
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RTC_LPD_OPT_XOSC_LPD = 2 << 13,
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RTC_LPD_OPT_F32K_CK_ALIVE = 3 << 13,
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RTC_LPD_OPT_MASK = 3 << 13
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RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
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RTC_LPD_OPT_EOSC_LPD = 1U << 13,
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RTC_LPD_OPT_XOSC_LPD = 2U << 13,
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RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
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RTC_LPD_OPT_MASK = 3U << 13
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};
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/* PMIC TOP Register Definition */
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@ -33,20 +33,19 @@ static int rtc_enable_dcxo(void)
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mdelay(1);
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if (!rtc_writeif_unlock()) { /* Unlock for reload */
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rtc_info("rtc_writeif_unlock() fail\n");
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rtc_info("rtc_writeif_unlock() failed\n");
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return 0;
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}
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rtc_read(RTC_OSC32CON, &osc32con);
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osc32con &= ~RTC_EMBCK_SRC_SEL;
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osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB;
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osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK
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| RTC_GPS_CKOUT_EN);
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osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB
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| RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION;
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if (!rtc_xosc_write(osc32con)) {
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rtc_info("rtc_xosc_write() fail\n");
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rtc_info("rtc_xosc_write() failed\n");
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return 0;
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}
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rtc_read(RTC_BBPU, &bbpu);
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rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
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rtc_write_trigger();
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rtc_read(RTC_CON, &con);
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rtc_read(RTC_OSC32CON, &osc32con);
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@ -197,12 +196,6 @@ int rtc_init(u8 recover)
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goto err;
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}
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/* using dcxo 32K clock */
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if (!rtc_enable_dcxo()) {
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ret = -RTC_STATUS_OSC_SETTING_FAIL;
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goto err;
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}
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if (recover)
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mdelay(20);
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@ -264,7 +257,7 @@ void poweroff(void)
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u16 bbpu;
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if (!rtc_writeif_unlock())
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rtc_info("rtc_writeif_unlock() fail\n");
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rtc_info("rtc_writeif_unlock() failed\n");
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/* pull PWRBB low */
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bbpu = RTC_BBPU_KEY | RTC_BBPU_RELOAD | RTC_BBPU_PWREN;
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rtc_write(RTC_BBPU, bbpu);
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@ -311,6 +304,10 @@ void rtc_boot(void)
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pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0);
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pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0);
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/* use dcxo 32K clock */
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if (!rtc_enable_dcxo())
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rtc_info("rtc_enable_dcxo() failed\n");
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rtc_boot_common();
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rtc_bbpu_power_on();
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}
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