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mediatek/mt8183: Enable RTC eosc calibration feature to save power 

When system shuts down, RTC enable eosc calibration feature to save
power. Then coreboot RTC driver needs to call rtc_enable_dcxo function
at every boot to switch RTC clock source to dcxo.

BUG=b:128467245
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Ran Bi 2019-04-17 15:43:14 +08:00 committed by Martin Roth
parent e458bcd099
commit fcfa35670a
3 changed files with 33 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/soc/mediatek/common/rtc.c
View File

@ -91,12 +91,15 @@ int rtc_xosc_write(u16 val)
u16 bbpu; u16 bbpu;
rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1); rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
udelay(200); if (!rtc_busy_wait())
return 0;
rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2); rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
udelay(200); if (!rtc_busy_wait())
return 0;
rtc_write(RTC_OSC32CON, val); rtc_write(RTC_OSC32CON, val);
udelay(200); if (!rtc_busy_wait())
return 0;
rtc_read(RTC_BBPU, &bbpu); rtc_read(RTC_BBPU, &bbpu);
bbpu |= RTC_BBPU_KEY | RTC_BBPU_RELOAD; bbpu |= RTC_BBPU_KEY | RTC_BBPU_RELOAD;

25
src/soc/mediatek/mt8183/include/soc/rtc.h
View File

@ -100,18 +100,25 @@ enum {
}; };
enum { enum {
RTC_EMBCK_SRC_SEL = 1 << 8, RTC_XOSCCALI_MASK = 0x1F << 0,
RTC_EMBCK_SEL_MODE = 3 << 6, RTC_XOSC32_ENB = 1U << 5,
RTC_XOSC32_ENB = 1 << 5, RTC_EMB_HW_MODE = 0U << 6,
RTC_REG_XOSC32_ENB = 1 << 15 RTC_EMB_K_EOSC32_MODE = 1U << 6,
RTC_EMB_SW_DCXO_MODE = 2U << 6,
RTC_EMB_SW_EOSC32_MODE = 3U << 6,
RTC_EMBCK_SEL_MODE_MASK = 3U << 6,
RTC_EMBCK_SRC_SEL = 1U << 8,
RTC_EMBCK_SEL_OPTION = 1U << 9,
RTC_GPS_CKOUT_EN = 1U << 10,
RTC_REG_XOSC32_ENB = 1U << 15
}; };
enum { enum {
RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0 << 13, RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
RTC_LPD_OPT_EOSC_LPD = 1 << 13, RTC_LPD_OPT_EOSC_LPD = 1U << 13,
RTC_LPD_OPT_XOSC_LPD = 2 << 13, RTC_LPD_OPT_XOSC_LPD = 2U << 13,
RTC_LPD_OPT_F32K_CK_ALIVE = 3 << 13, RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
RTC_LPD_OPT_MASK = 3 << 13 RTC_LPD_OPT_MASK = 3U << 13
}; };
/* PMIC TOP Register Definition */ /* PMIC TOP Register Definition */

25
src/soc/mediatek/mt8183/rtc.c
View File

@ -33,20 +33,19 @@ static int rtc_enable_dcxo(void)
mdelay(1); mdelay(1);
if (!rtc_writeif_unlock()) { /* Unlock for reload */ if (!rtc_writeif_unlock()) { /* Unlock for reload */
rtc_info("rtc_writeif_unlock() fail\n"); rtc_info("rtc_writeif_unlock() failed\n");
return 0; return 0;
} }
rtc_read(RTC_OSC32CON, &osc32con); rtc_read(RTC_OSC32CON, &osc32con);
osc32con &= ~RTC_EMBCK_SRC_SEL; osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK
osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB; | RTC_GPS_CKOUT_EN);
osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB
| RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION;
if (!rtc_xosc_write(osc32con)) { if (!rtc_xosc_write(osc32con)) {
rtc_info("rtc_xosc_write() fail\n"); rtc_info("rtc_xosc_write() failed\n");
return 0; return 0;
} }
rtc_read(RTC_BBPU, &bbpu);
rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
rtc_write_trigger();
rtc_read(RTC_CON, &con); rtc_read(RTC_CON, &con);
rtc_read(RTC_OSC32CON, &osc32con); rtc_read(RTC_OSC32CON, &osc32con);
@ -197,12 +196,6 @@ int rtc_init(u8 recover)
goto err; goto err;
} }
/* using dcxo 32K clock */
if (!rtc_enable_dcxo()) {
ret = -RTC_STATUS_OSC_SETTING_FAIL;
goto err;
}
if (recover) if (recover)
mdelay(20); mdelay(20);
@ -264,7 +257,7 @@ void poweroff(void)
u16 bbpu; u16 bbpu;
if (!rtc_writeif_unlock()) if (!rtc_writeif_unlock())
rtc_info("rtc_writeif_unlock() fail\n"); rtc_info("rtc_writeif_unlock() failed\n");
/* pull PWRBB low */ /* pull PWRBB low */
bbpu = RTC_BBPU_KEY | RTC_BBPU_RELOAD | RTC_BBPU_PWREN; bbpu = RTC_BBPU_KEY | RTC_BBPU_RELOAD | RTC_BBPU_PWREN;
rtc_write(RTC_BBPU, bbpu); rtc_write(RTC_BBPU, bbpu);
@ -311,6 +304,10 @@ void rtc_boot(void)
pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0); pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0);
pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0); pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0);
/* use dcxo 32K clock */
if (!rtc_enable_dcxo())
rtc_info("rtc_enable_dcxo() failed\n");
rtc_boot_common(); rtc_boot_common();
rtc_bbpu_power_on(); rtc_bbpu_power_on();
} }