From fd078d85d01810a4f03a8c21d454c04d9e2d3ae4 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Wed, 11 Aug 2021 13:27:45 -0600 Subject: [PATCH] soc/amd: Show SPI settings in bootblock BUG=b:194919326 TEST=See SPI settings in bootblock Signed-off-by: Martin Roth Change-Id: I8ee8981986990240b09414cde8b84d9b109cb5b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56961 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Felix Held Reviewed-by: Karthik Ramasubramanian --- src/soc/amd/cezanne/early_fch.c | 1 + src/soc/amd/picasso/early_fch.c | 1 + src/soc/amd/stoneyridge/southbridge.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 9da154cd2b..16a8a53c75 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -73,6 +73,7 @@ void fch_early_init(void) pm_set_power_failure_state(); fch_print_pmxc0_status(); i2c_soc_early_init(); + show_spi_speeds_and_modes(); if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) lpc_disable_spi_rom_sharing(); diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index 88011c1fc3..110718e2e1 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -75,6 +75,7 @@ void fch_early_init(void) pm_set_power_failure_state(); fch_print_pmxc0_status(); i2c_soc_early_init(); + show_spi_speeds_and_modes(); if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) lpc_disable_spi_rom_sharing(); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 5f5fc72bfc..7493770fac 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -357,6 +357,7 @@ void bootblock_fch_init(void) { pm_set_power_failure_state(); fch_print_pmxc0_status(); + show_spi_speeds_and_modes(); } static void fch_init_acpi_ports(void)