nb/intel/sandybridge/raminit: Split raminit.c
Split raminit.c into smaller parts. Move all functions that will be used by chip-specific code into raminit_common.c. The chip-specific changes includes new configuration values for IvyBridge and 100Mhz reference clock support, including new frequencies. No functionality is changed. Tested on Lenovo T420. Change-Id: If7bb5949f4b771430f3dba1b754ad241a7e8426b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17604 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -26,6 +26,7 @@ ramstage-y += acpi.c
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romstage-y += ram_calc.c
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ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
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romstage-y += raminit.c
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romstage-y += raminit_common.c
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romstage-y += ../../../device/dram/ddr3.c
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else
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romstage-y += raminit_mrc.c
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@ -0,0 +1,180 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Damien Zammit <damien@zamaudio.com>
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* Copyright (C) 2014 Vladimir Serbinenko <phcoder@gmail.com>
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* Copyright (C) 2016 Patrick Rudolph <siro@das-labor.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef RAMINIT_COMMON_H
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#define RAMINIT_COMMON_H
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#define BASEFREQ 133
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#define tDLLK 512
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#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0)
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#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4)
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#define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5)
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#define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6)
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#define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7)
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#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0)
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#define IS_IVY_CPU_C(x) ((x & 0xf) == 4)
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#define IS_IVY_CPU_K(x) ((x & 0xf) == 5)
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#define IS_IVY_CPU_D(x) ((x & 0xf) == 6)
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#define IS_IVY_CPU_E(x) ((x & 0xf) >= 8)
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#define NUM_CHANNELS 2
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#define NUM_SLOTRANKS 4
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#define NUM_SLOTS 2
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#define NUM_LANES 8
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/* FIXME: Vendor BIOS uses 64 but our algorithms are less
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performant and even 1 seems to be enough in practice. */
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#define NUM_PATTERNS 4
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typedef struct odtmap_st {
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u16 rttwr;
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u16 rttnom;
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} odtmap;
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typedef struct dimm_info_st {
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dimm_attr dimm[NUM_CHANNELS][NUM_SLOTS];
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} dimm_info;
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struct ram_rank_timings {
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/* Register 4024. One byte per slotrank. */
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u8 val_4024;
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/* Register 4028. One nibble per slotrank. */
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u8 val_4028;
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int val_320c;
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struct ram_lane_timings {
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/* lane register offset 0x10. */
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u16 timA; /* bits 0 - 5, bits 16 - 18 */
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u8 rising; /* bits 8 - 14 */
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u8 falling; /* bits 20 - 26. */
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/* lane register offset 0x20. */
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int timC; /* bit 0 - 5, 19. */
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u16 timB; /* bits 8 - 13, 15 - 17. */
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} lanes[NUM_LANES];
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};
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struct ramctr_timing_st;
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typedef struct ramctr_timing_st {
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u16 spd_crc[NUM_CHANNELS][NUM_SLOTS];
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int mobile;
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u16 cas_supported;
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/* tLatencies are in units of ns, scaled by x256 */
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u32 tCK;
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u32 tAA;
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u32 tWR;
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u32 tRCD;
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u32 tRRD;
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u32 tRP;
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u32 tRAS;
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u32 tRFC;
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u32 tWTR;
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u32 tRTP;
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u32 tFAW;
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/* Latencies in terms of clock cycles
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* They are saved separately as they are needed for DRAM MRS commands*/
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u8 CAS; /* CAS read latency */
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u8 CWL; /* CAS write latency */
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u32 tREFI;
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u32 tMOD;
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u32 tXSOffset;
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u32 tWLO;
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u32 tCKE;
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u32 tXPDLL;
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u32 tXP;
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u32 tAONPD;
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u16 reg_5064b0; /* bits 0-11. */
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u8 rankmap[NUM_CHANNELS];
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int ref_card_offset[NUM_CHANNELS];
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u32 mad_dimm[NUM_CHANNELS];
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int channel_size_mb[NUM_CHANNELS];
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u32 cmd_stretch[NUM_CHANNELS];
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int reg_c14_offset;
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int reg_320c_range_threshold;
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int edge_offset[3];
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int timC_offset[3];
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int extended_temperature_range;
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int auto_self_refresh;
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int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS];
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struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS];
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dimm_info info;
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} ramctr_timing;
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#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
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#define NORTHBRIDGE PCI_DEV(0, 0x0, 0)
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#define FOR_ALL_LANES for (lane = 0; lane < NUM_LANES; lane++)
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#define FOR_ALL_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++)
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#define FOR_ALL_POPULATED_RANKS for (slotrank = 0; slotrank < NUM_SLOTRANKS; slotrank++) if (ctrl->rankmap[channel] & (1 << slotrank))
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#define FOR_ALL_POPULATED_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) if (ctrl->rankmap[channel])
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#define MAX_EDGE_TIMING 71
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#define MAX_TIMC 127
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#define MAX_TIMB 511
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#define MAX_TIMA 127
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#define MAX_CAS 18
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#define MIN_CAS 4
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#define MAKE_ERR ((channel<<16)|(slotrank<<8)|1)
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#define GET_ERR_CHANNEL(x) (x>>16)
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#define MC_BIOS_REQ 0x5e00
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#define MC_BIOS_DATA 0x5e04
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u8 get_CWL(u32 tCK);
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void dram_mrscommands(ramctr_timing * ctrl);
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void program_timings(ramctr_timing * ctrl, int channel);
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void dram_find_common_params(ramctr_timing *ctrl);
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void dram_xover(ramctr_timing * ctrl);
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void dram_timing_regs(ramctr_timing * ctrl);
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void dram_dimm_mapping(ramctr_timing *ctrl);
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void dram_dimm_set_mapping(ramctr_timing * ctrl);
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void dram_zones(ramctr_timing * ctrl, int training);
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unsigned int get_mem_min_tck(void);
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void dram_memorymap(ramctr_timing * ctrl, int me_uma_size);
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void dram_jedecreset(ramctr_timing * ctrl);
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int read_training(ramctr_timing * ctrl);
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int write_training(ramctr_timing * ctrl);
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int command_training(ramctr_timing *ctrl);
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int discover_edges(ramctr_timing *ctrl);
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int discover_edges_write(ramctr_timing *ctrl);
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int discover_timC_write(ramctr_timing *ctrl);
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void normalize_training(ramctr_timing * ctrl);
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void write_controller_mr(ramctr_timing * ctrl);
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int channel_test(ramctr_timing *ctrl);
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void set_scrambling_seed(ramctr_timing * ctrl);
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void set_4f8c(void);
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void prepare_training(ramctr_timing * ctrl);
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void set_4008c(ramctr_timing * ctrl);
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void set_42a0(ramctr_timing * ctrl);
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void final_registers(ramctr_timing * ctrl);
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void restore_timings(ramctr_timing * ctrl);
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#endif
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