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mb/cavium/cn8100_sff_evb: adjust fmap 

Adjust the default fmap description file.
Tested on real hardware.

Change-Id: I46165eb27314a500187bcd24e3e201cf6a3175e7
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29596
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marcello Sylvester Bauer 2018-11-12 13:54:17 +01:00 committed by Patrick Georgi
parent 978f47add8
commit fd7fe58e60
2 changed files with 8 additions and 17 deletions
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2
src/mainboard/cavium/cn8100_sff_evb/Kconfig
View File

@ -17,7 +17,7 @@ if BOARD_CAVIUM_CN8100_SFF_EVB
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select BOARD_ROMSIZE_KB_8192
select COMMON_CBFS_SPI_WRAPPER
select RTC
select SOC_CAVIUM_CN81XX

23
src/mainboard/cavium/cn8100_sff_evb/board.fmd
View File

@ -1,24 +1,15 @@
FLASH@0x0 8M {
WP_RO@0x0 0x400000 {
RO_SECTION@0x0 0x200000 {
WP_RO@0x0 0x800000 {
RO_SECTION@0x0 0x7fc000 {
# 0 - 0x10000 is free for firmware usage.
# bootblock starts at 0x20000
FMAP@0x0 0x1000
# bootblock includes trusted/non-trusted CLIB, CSIB,
# and BL1FWs packaged in
# src/soc/cavium/common/Makefile.inc.
BOOTBLOCK@0x10000 0x70000
FMAP@0x90000 0x1000
COREBOOT(CBFS)@0x100000 0x100000
COREBOOT(CBFS)@0x80000 0x77c000
}
RO_VPD@0x7fc000 0x4000
}
RW_SECTION_A@0x400000 0xe8000 {
VBLOCK_A@0x0 0x2000
FW_MAIN_A(CBFS)@0x2000 0xe5f00
RW_FWID_A@0xe7f00 0x100
}
RW_UNUSED@0x4e8000 0x8000
RW_ELOG@0x5d8000 0x1000
RW_SHARED@0x5e0000 0x10000 {
SHARED_DATA@0x0 0x10000
}
RW_NVRAM@0x5f0000 0x10000
CONSOLE@0x700000 0x100000
}