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src/mb: Remove unneeded spaces before/after tabs 

Change-Id: I02979a0632a7b356985f96c3ba239daba178b4e3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39989
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2020-03-31 21:42:02 +02:00 committed by Angel Pons
parent a0722870a8
commit fd8de1860d
17 changed files with 36 additions and 36 deletions
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6
src/mainboard/51nb/x210/devicetree.cb
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@ -107,9 +107,9 @@ chip soc/intel/skylake
register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)" # FPR
register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # INT
register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)" # FPR
register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # INT
register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Webcam
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # mPCIe / WiFi Port

2
src/mainboard/amd/south_station/acpi/gpe.asl
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@ -51,7 +51,7 @@ Scope(\_GPE) { /* Start Scope GPE */
/* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
}
} /* End Scope GPE */
} /* End Scope GPE */
/* Contains the GPEs for USB overcurrent */
#include "usb_oc.asl"

2
src/mainboard/amd/south_station/acpi/sleep.asl
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@ -37,7 +37,7 @@ Method(\_PTS, 1) {
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE)
* Store(0,\_SB.PWDE)
*}
*/

2
src/mainboard/amd/south_station/acpi/usb_oc.asl
View File

@ -25,7 +25,7 @@ Name(UOM9, 6)
Method(UCOC, 0) {
Sleep(20)
Store(0x13,CMTI)
Store(0x13,CMTI)
Store(0,GPSL)
}

2
src/mainboard/amd/union_station/acpi/gpe.asl
View File

@ -51,7 +51,7 @@ Scope(\_GPE) { /* Start Scope GPE */
/* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
}
} /* End Scope GPE */
} /* End Scope GPE */
/* Contains the GPEs for USB overcurrent */
#include "usb_oc.asl"

2
src/mainboard/amd/union_station/acpi/sleep.asl
View File

@ -37,7 +37,7 @@ Method(\_PTS, 1) {
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE)
* Store(0,\_SB.PWDE)
*}
*/

2
src/mainboard/amd/union_station/acpi/usb_oc.asl
View File

@ -25,7 +25,7 @@ Name(UOM9, 6)
Method(UCOC, 0) {
Sleep(20)
Store(0x13,CMTI)
Store(0x13,CMTI)
Store(0,GPSL)
}

2
src/mainboard/asus/p5qc/variants/p5q/devicetree.cb
View File

@ -55,7 +55,7 @@ chip northbridge/intel/x4x # Northbridge
device pci 1d.2 on end # USB
device pci 1d.7 on end # USB
device pci 1e.0 on end # PCI bridge
device pci 1f.0 on # LPC bridge
device pci 1f.0 on # LPC bridge
chip superio/winbond/w83667hg-a # Super I/O
device pnp 2e.0 on # FDC
# Global registers

2
src/mainboard/emulation/qemu-aarch64/bootblock_custom.S
View File

@ -24,7 +24,7 @@ ENTRY(_start)
dmb sy
/* Calculate relocation offset between bootblock in flash and in DRAM. */
ldr x0, =_flash
ldr x0, =_flash
ldr x1, =_bootblock
sub x1, x1, x0

2
src/mainboard/google/volteer/acpi/mipi_camera.asl
View File

@ -290,7 +290,7 @@ Scope (\_SB.PCI0.I2C3)
"endpoint",
Zero
},
Package (0x02)
Package (0x02)
{
"clock-lanes",
Zero

2
src/mainboard/intel/tglrvp/acpi/mipi_camera.asl
View File

@ -281,7 +281,7 @@ Scope (\_SB.PCI0.I2C3)
"endpoint",
Zero
},
Package (0x02)
Package (0x02)
{
"clock-lanes",
Zero

4
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -154,7 +154,7 @@ chip soc/intel/tigerlake
end
device pci 12.6 off end # GSPI2 0x34FB
device pci 13.0 off end # GSPI3 0xA0FD
device pci 14.0 on end # USB3.1 xHCI 0xA0ED
device pci 14.0 on end # USB3.1 xHCI 0xA0ED
device pci 14.1 on end # USB3.1 xDCI 0xA0EE
device pci 14.2 on end # Shared RAM 0xA0EF
chip drivers/intel/wifi
@ -162,7 +162,7 @@ chip soc/intel/tigerlake
device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3
end
device pci 15.0 on # I2C0 0xA0E8
device pci 15.0 on # I2C0 0xA0E8
chip drivers/i2c/max98373
register "vmon_slot_no" = "4"
register "imon_slot_no" = "5"

4
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -150,7 +150,7 @@ chip soc/intel/tigerlake
end
device pci 12.6 off end # GSPI2 0x34FB
device pci 13.0 off end # GSPI3 0xA0FD
device pci 14.0 on end # USB3.1 xHCI 0xA0ED
device pci 14.0 on end # USB3.1 xHCI 0xA0ED
device pci 14.1 on end # USB3.1 xDCI 0xA0EE
device pci 14.2 on end # Shared RAM 0xA0EF
chip drivers/intel/wifi
@ -158,7 +158,7 @@ chip soc/intel/tigerlake
device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3
end
device pci 15.0 on # I2C0 0xA0E8
device pci 15.0 on # I2C0 0xA0E8
chip drivers/i2c/max98373
register "vmon_slot_no" = "4"
register "imon_slot_no" = "5"

12
src/mainboard/lenovo/t400/variants/r500/overridetree.cb
View File

@ -5,8 +5,8 @@ chip northbridge/intel/gm45
register "sata_clock_request" = "1"
# Enable PCIe ports 1,2,4,5,6 as slots (Mini * PCIe).
register "pcie_slot_implemented" = "0x3b"
# Set power limits to 10 * 10^0 watts.
# Maybe we should set less for Mini PCIe.
# Set power limits to 10 * 10^0 watts.
# Maybe we should set less for Mini PCIe.
register "pcie_power_limits" = "{ { 41, 0 }, { 41, 0 }, { 0, 0 }, { 41, 0 }, { 41, 0 }, { 41, 0 } }"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 1, 0, 0 }"
device pci 19.0 off end # LAN
@ -29,9 +29,9 @@ chip northbridge/intel/gm45
register "eventb_enable" = "0x00"
end
end
device pci 1f.3 on # SMBus
subsystemid 0x17aa 0x20f9
ioapic_irq 2 INTC 0x12
device pci 1f.3 on # SMBus
subsystemid 0x17aa 0x20f9
ioapic_irq 2 INTC 0x12
# eeprom, 4 virtual devices, same chip
chip drivers/i2c/at24rf08c
device i2c 54 on end
@ -39,7 +39,7 @@ chip northbridge/intel/gm45
device i2c 56 on end
device i2c 57 on end
end
end
end
end
end
end

8
src/mainboard/lenovo/t400/variants/t400/overridetree.cb
View File

@ -23,9 +23,9 @@ chip northbridge/intel/gm45
register "has_thinker1" = "0"
end
end
device pci 1f.3 on # SMBus
subsystemid 0x17aa 0x20f9
ioapic_irq 2 INTC 0x12
device pci 1f.3 on # SMBus
subsystemid 0x17aa 0x20f9
ioapic_irq 2 INTC 0x12
# eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c
device i2c 54 on end
@ -37,7 +37,7 @@ chip northbridge/intel/gm45
device i2c 5e on end
device i2c 5f on end
end
end
end
end
end
end

10
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
View File

@ -12,11 +12,11 @@ chip soc/intel/skylake
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
# PCIe configuration
register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4
register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5
register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1
register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2
register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA
register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4
register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5
register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1
register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2
register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA
# USB configuration
# USB0/1

8
src/mainboard/system76/lemp9/devicetree.cb
View File

@ -74,11 +74,11 @@ chip soc/intel/cannonlake
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 3
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 3
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera
register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
@ -90,7 +90,7 @@ chip soc/intel/cannonlake
register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # NC