treewide: Get rid of CONFIG_AZALIA_MAX_CODECS

Get rid of Kconfig symbol introduced at commit 5d31dfa8
High Definition Audio Specification Revision 1.0a says, there
are 15 SDIWAKE bits.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ib8b656daca52e21cb0c7120b208a2acdd88625e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62202
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes Haouas 2022-02-20 11:09:07 +01:00 committed by Felix Held
parent 7f7ac206f8
commit fd93cff329
10 changed files with 5 additions and 38 deletions

View File

@ -527,14 +527,6 @@ config AZALIA_PLUGIN_SUPPORT
bool
default n
config AZALIA_MAX_CODECS
int
depends on AZALIA_PLUGIN_SUPPORT
default 3
range 1 15
help
The maximum number of codecs supported on a single HD Audio controller.
config AZALIA_LOCK_DOWN_R_WO_GCAP
def_bool n
depends on AZALIA_PLUGIN_SUPPORT

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@ -50,7 +50,6 @@ int azalia_exit_reset(u8 *base)
static u16 codec_detect(u8 *base)
{
struct stopwatch sw;
const u16 codec_mask = (1 << CONFIG_AZALIA_MAX_CODECS) - 1;
u16 reg16;
if (azalia_exit_reset(base) < 0)
@ -61,9 +60,9 @@ static u16 codec_detect(u8 *base)
write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
}
/* clear STATESTS bits (BAR + 0xe)[2:0] */
/* clear STATESTS bits (BAR + 0x0e)[14:0] */
reg16 = read16(base + HDA_STATESTS_REG);
reg16 |= codec_mask;
reg16 |= 0x7fff;
write16(base + HDA_STATESTS_REG, reg16);
/* Wait for readback of register to
@ -86,9 +85,9 @@ static u16 codec_detect(u8 *base)
if (azalia_exit_reset(base) < 0)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */
/* Read in Codec location (BAR + 0x0e)[14:0] */
reg16 = read16(base + HDA_STATESTS_REG);
reg16 &= codec_mask;
reg16 &= 0x7fff;
if (!reg16)
goto no_codec;
@ -274,7 +273,7 @@ void azalia_codecs_init(u8 *base, u16 codec_mask)
{
int i;
for (i = CONFIG_AZALIA_MAX_CODECS - 1; i >= 0; i--) {
for (i = 14; i >= 0; i--) {
if (codec_mask & (1 << i))
azalia_codec_init(base, i, cim_verb_data, cim_verb_data_size);
}

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@ -24,9 +24,6 @@ config PCH_SPECIFIC_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
select SPI_FLASH
config AZALIA_MAX_CODECS
default 4
config EHCI_BAR
hex
default 0xd8000000

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@ -9,6 +9,3 @@ config SOC_INTEL_COMMON_BLOCK_HDA_VERB
select AZALIA_LOCK_DOWN_R_WO_GCAP
help
Enable initialization of HDA codecs.
config AZALIA_MAX_CODECS
default 4 if SOC_INTEL_COMMON_BLOCK_HDA_VERB

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@ -37,9 +37,6 @@ config SOUTH_BRIDGE_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
config AZALIA_MAX_CODECS
default 4
config EHCI_BAR
hex
default 0xfef00000

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@ -25,9 +25,6 @@ config SOUTHBRIDGE_INTEL_I82801GX
if SOUTHBRIDGE_INTEL_I82801GX
config AZALIA_MAX_CODECS
default 3
config EHCI_BAR
hex
default 0xfef00000

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@ -24,9 +24,6 @@ config SOUTHBRIDGE_INTEL_I82801IX
if SOUTHBRIDGE_INTEL_I82801IX
config AZALIA_MAX_CODECS
default 4
config EHCI_BAR
hex
default 0xfef00000

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@ -25,9 +25,6 @@ config SOUTHBRIDGE_INTEL_I82801JX
if SOUTHBRIDGE_INTEL_I82801JX
config AZALIA_MAX_CODECS
default 4
config EHCI_BAR
hex
default 0xfef00000

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@ -33,9 +33,6 @@ config SOUTH_BRIDGE_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
config AZALIA_MAX_CODECS
default 4
config EHCI_BAR
hex
default 0xfef00000

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@ -41,9 +41,6 @@ config INTEL_LYNXPOINT_LP
help
Set this option to y for LynxPoint LP (Haswell ULT).
config AZALIA_MAX_CODECS
default 4
config EHCI_BAR
hex
default 0xe8000000