Use the coreboot pci config read/write functions instead of direct cf8/cfc
access. The fam10 pci functions will use mmio and do not have SMP pci access issues. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -2472,22 +2472,13 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat,
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u32 Get_NB32(u32 dev, u32 reg)
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{
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u32 addr;
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addr = (dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16);
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outl((1<<31) | (addr & ~3), 0xcf8);
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return inl(0xcfc);
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return pci_read_config32(dev, reg);
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}
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void Set_NB32(u32 dev, u32 reg, u32 val)
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{
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u32 addr;
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addr = (dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16);
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outl((1<<31) | (addr & ~3), 0xcf8);
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outl(val, 0xcfc);
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pci_write_config32(dev, reg, val);
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}
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