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Use the coreboot pci config read/write functions instead of direct cf8/cfc 

access. The fam10 pci functions will use mmio and do not have SMP pci access
issues.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones 2009-09-14 17:00:04 +00:00 committed by Marc Jones
parent fea8a4f8d3
commit fd9c9b8ff8
1 changed files with 2 additions and 11 deletions
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13
src/northbridge/amd/amdmct/mct/mct_d.c
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@ -2472,22 +2472,13 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat,
u32 Get_NB32(u32 dev, u32 reg) u32 Get_NB32(u32 dev, u32 reg)
{ {
u32 addr; return pci_read_config32(dev, reg);
addr = (dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16);
outl((1<<31) | (addr & ~3), 0xcf8);
return inl(0xcfc);
} }
void Set_NB32(u32 dev, u32 reg, u32 val) void Set_NB32(u32 dev, u32 reg, u32 val)
{ {
u32 addr; pci_write_config32(dev, reg, val);
addr = (dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16);
outl((1<<31) | (addr & ~3), 0xcf8);
outl(val, 0xcfc);
} }