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soc/intel/denverton_ns: Allow using FSP repo 

This commit is adding a dependency check for the FSP_USE_REPO
config option which so far was not able to deal with Denverton
systems.

Change-Id: I615305da5865bef305f560f5c90482cf0937b25a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
This commit is contained in:
Felix Singer 2019-01-15 07:29:57 +01:00 committed by Patrick Georgi
parent 2d7bb7e141
commit fdccfc6267
3 changed files with 11 additions and 3 deletions
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3
src/drivers/intel/fsp2_0/Kconfig
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@ -55,7 +55,8 @@ config FSP_USE_REPO
depends on ADD_FSP_BINARIES depends on ADD_FSP_BINARIES
depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \
SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \
SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE || \
SOC_INTEL_DENVERTON_NS
help help
When selecting this option, the SoC must set FSP_HEADER_PATH When selecting this option, the SoC must set FSP_HEADER_PATH
and FSP_FD_PATH correctly so FSP splitting works. and FSP_FD_PATH correctly so FSP splitting works.

9
src/soc/intel/denverton_ns/Kconfig
View File

@ -79,6 +79,15 @@ config FSP_S_ADDR
help help
The memory location of the Intel FSP-S binary for this platform. The memory location of the Intel FSP-S binary for this platform.
config FSP_HEADER_PATH
string
default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/"
config FSP_FD_PATH
string
depends on FSP_USE_REPO
default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd"
# CAR memory layout on DENVERTON_NS hardware: # CAR memory layout on DENVERTON_NS hardware:
## CAR base address - 0xfef00000 ## CAR base address - 0xfef00000
## CAR size 1MB - 0x100 (0xfff00) ## CAR size 1MB - 0x100 (0xfff00)

2
src/soc/intel/denverton_ns/Makefile.inc
View File

@ -86,10 +86,8 @@ verstage-y += tsc_freq.c
verstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c verstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
CPPFLAGS_common += -I$(src)/soc/intel/denverton_ns/include CPPFLAGS_common += -I$(src)/soc/intel/denverton_ns/include
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/denverton_ns
##Set FSP binary blobs memory location ##Set FSP binary blobs memory location
$(call strip_quotes,$(CONFIG_FSP_T_CBFS))-options := -b $(CONFIG_FSP_T_ADDR) --xip $(call strip_quotes,$(CONFIG_FSP_T_CBFS))-options := -b $(CONFIG_FSP_T_ADDR) --xip
$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) --xip $(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) --xip
$(call strip_quotes,$(CONFIG_FSP_S_CBFS))-options := -b $(CONFIG_FSP_S_ADDR) --xip $(call strip_quotes,$(CONFIG_FSP_S_CBFS))-options := -b $(CONFIG_FSP_S_ADDR) --xip