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superio/smsc/smscsuperio: Make romstage linkable with header 

Rewrite smsc/smscsuperio romstage component to be more consistent and
provide header there-by removing #include's of early_serial.c's in
mainboard's.

Change-Id: I572e0c76422f09d4de88935a36c0a59e5350e6e0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5915
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Edward O'Callaghan 2014-06-02 07:58:14 +10:00 committed by Kyösti Mälkki
parent 8f45761a67
commit fdceb48b36
15 changed files with 72 additions and 23 deletions
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2
src/mainboard/aaeon/pfm-540i_revb/romstage.c
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@ -35,7 +35,7 @@
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
#include "superio/smsc/smscsuperio/early_serial.c"
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include "northbridge/amd/lx/raminit.h"
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)

2
src/mainboard/asus/mew-am/romstage.c
View File

@ -29,7 +29,7 @@
#include "northbridge/intel/i82810/raminit.h"
#include "drivers/pc80/udelay_io.c"
#include "cpu/x86/bist.h"
#include "superio/smsc/smscsuperio/early_serial.c"
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)

2
src/mainboard/biostar/m6tba/romstage.c
View File

@ -30,7 +30,7 @@
#include "drivers/pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
#include "superio/smsc/smscsuperio/early_serial.c"
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)

2
src/mainboard/iei/pm-lx2-800-r10/romstage.c
View File

@ -33,7 +33,7 @@
#include <southbridge/amd/cs5536/cs5536.h>
#include <southbridge/amd/cs5536/early_smbus.c>
#include <southbridge/amd/cs5536/early_setup.c>
#include <superio/smsc/smscsuperio/early_serial.c>
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include <northbridge/amd/lx/raminit.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)

2
src/mainboard/intel/d810e2cb/romstage.c
View File

@ -29,7 +29,7 @@
#include "northbridge/intel/i82810/raminit.h"
#include "drivers/pc80/udelay_io.c"
#include "cpu/x86/bist.h"
#include "superio/smsc/smscsuperio/early_serial.c"
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include "gpio.c"
#include <lib.h>

2
src/mainboard/intel/eagleheights/romstage.c
View File

@ -34,7 +34,7 @@
#include "southbridge/intel/i3100/early_lpc.c"
#include "southbridge/intel/i3100/reset.c"
#include "superio/intel/i3100/early_serial.c"
#include "superio/smsc/smscsuperio/early_serial.c"
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include "northbridge/intel/i3100/i3100.h"
#include "southbridge/intel/i3100/i3100.h"

2
src/mainboard/lippert/frontrunner-af/romstage.c
View File

@ -32,7 +32,7 @@
#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include "superio/smsc/smscsuperio/early_serial.c"
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include "cpu/x86/lapic.h"
#include <cpu/x86/cache.h>
#include <sb_cimx.h>

2
src/mainboard/mitac/6513wu/romstage.c
View File

@ -30,7 +30,7 @@
#include "drivers/pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
#include "superio/smsc/smscsuperio/early_serial.c"
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)

2
src/mainboard/nec/powermate2000/romstage.c
View File

@ -25,7 +25,7 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "superio/smsc/smscsuperio/early_serial.c"
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include "northbridge/intel/i82810/raminit.h"
#include "cpu/x86/bist.h"
#include "southbridge/intel/i82801ax/i82801ax.h"

2
src/mainboard/nokia/ip530/romstage.c
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@ -30,7 +30,7 @@
#include "drivers/pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
#include "superio/smsc/smscsuperio/early_serial.c"
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)

2
src/mainboard/rca/rm4100/romstage.c
View File

@ -27,7 +27,7 @@
#include "drivers/pc80/udelay_io.c"
#include <console/console.h>
#include <lib.h>
#include "superio/smsc/smscsuperio/early_serial.c"
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include "northbridge/intel/i82830/raminit.h"
#include "northbridge/intel/i82830/memory_initialized.c"
#include "southbridge/intel/i82801dx/i82801dx.h"

2
src/mainboard/thomson/ip1000/romstage.c
View File

@ -27,7 +27,7 @@
#include "drivers/pc80/udelay_io.c"
#include <console/console.h>
#include <lib.h>
#include "superio/smsc/smscsuperio/early_serial.c"
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include "northbridge/intel/i82830/raminit.h"
#include "northbridge/intel/i82830/memory_initialized.c"
#include "southbridge/intel/i82801dx/i82801dx.h"

2
src/superio/smsc/smscsuperio/Makefile.inc
View File

@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
romstage-$(CONFIG_SUPERIO_SMSC_SMSCSUPERIO) += early_serial.c
ramstage-$(CONFIG_SUPERIO_SMSC_SMSCSUPERIO) += superio.c

34
src/superio/smsc/smscsuperio/early_serial.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -20,12 +21,27 @@
#include <arch/io.h>
#include <device/pnp_def.h>
#include <stdint.h>
#include "smscsuperio.h"
#define SMSC_ENTRY_KEY 0x55
#define SMSC_EXIT_KEY 0xAA
/* Enable configuration: pass entry key '0x87' into index port dev. */
static void pnp_enter_conf_state(device_t dev)
{
u16 port = dev >> 8;
outb(SMSC_ENTRY_KEY, port);
}
/* Disable configuration: pass exit key '0xAA' into index port dev. */
static void pnp_exit_conf_state(device_t dev)
{
u16 port = dev >> 8;
outb(SMSC_EXIT_KEY, port);
}
/* All known/supported SMSC Super I/Os have the same logical device IDs
* for the serial ports (COM1, COM2).
*/
#define SMSCSUPERIO_SP1 4 /* Com1 */
#define SMSCSUPERIO_SP2 5 /* Com2 */
/**
* Enable the specified serial port.
@ -33,14 +49,12 @@
* @param dev The device to use.
* @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8).
*/
static inline void smscsuperio_enable_serial(device_t dev, u16 iobase)
void smscsuperio_enable_serial(device_t dev, u16 iobase)
{
u16 port = dev >> 8;
outb(0x55, port); /* Enter the configuration state. */
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
outb(0xaa, port); /* Exit the configuration state. */
pnp_exit_conf_state(dev);
}

35
src/superio/smsc/smscsuperio/smscsuperio.h Normal file
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@ -0,0 +1,35 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SUPERIO_SMSC_SMSCSUPERIO_H
#define SUPERIO_SMSC_SMSCSUPERIO_H
#include <arch/io.h>
#include <stdint.h>
/* All known/supported SMSC Super I/Os have the same logical device IDs
* for the serial ports (COM1, COM2).
*/
#define SMSCSUPERIO_SP1 4 /* Com1 */
#define SMSCSUPERIO_SP2 5 /* Com2 */
void smscsuperio_enable_serial(device_t dev, u16 iobase);
#endif /* SUPERIO_SMSC_SMSCSUPERIO_H */