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Sorry for this. I fixed that reverting the change for ROMCC. 

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek 2010-05-16 22:26:25 +00:00
parent beba99045c
commit fdddce3b92
1 changed files with 28 additions and 0 deletions
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28
src/include/cpu/x86/cache.h
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@ -23,6 +23,17 @@
/* the memory clobber prevents the GCC from reordering the read/write order
of CR0 */
*/
#if defined(__GNUC__)
/*
Need this because ROMCC fails here with:
cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33:
0x1559920 asm Internal compiler error: lhs 1 regcm == 0
*/
static inline unsigned long read_cr0(void)
{
unsigned long cr0;
@ -35,6 +46,23 @@ static inline void write_cr0(unsigned long cr0)
asm volatile ("movl %0, %%cr0" : : "r" (cr0) : "memory");
}
#else
static inline unsigned long read_cr0(void)
{
unsigned long cr0;
asm volatile ("movl %%cr0, %0" : "=r" (cr0));
return cr0;
}
static inline void write_cr0(unsigned long cr0)
{
asm volatile ("movl %0, %%cr0" : : "r" (cr0));
}
#endif
static inline void invd(void)
{
asm volatile("invd" ::: "memory");