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- See Issue Tracker id-12 "lnxi-patch-12". 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Jason Schildt 2005-10-25 21:45:17 +00:00
parent cf6df2afb5
commit fddf46f275
20 changed files with 68 additions and 719 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/mainboard/Iwill/DK8S2/auto.c
View File

@ -23,6 +23,8 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -161,19 +163,7 @@ static void main(unsigned long bist)
unsigned nodeid;
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
/* Has this cpu already booted? */
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
if (!boot_cpu()) {
stop_this_cpu();
}
k8_init_and_stop_secondaries();
}
/* Setup the console */
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);

15
src/mainboard/Iwill/DK8X/auto.c
View File

@ -20,9 +20,11 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
@ -163,18 +165,7 @@ static void main(unsigned long bist)
unsigned nodeid;
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
/* Has this cpu already booted? */
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
if (!boot_cpu()) {
stop_this_cpu();
}
k8_init_and_stop_secondaries();
}
/* Setup the console */
pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);

17
src/mainboard/amd/quartet/auto.c
View File

@ -26,6 +26,7 @@
#include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
@ -212,21 +213,7 @@ static void main(unsigned long bist)
unsigned nodeid;
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
nodeid = lapicid() & 0xf;
/* Has this cpu already booted? */
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
if (!boot_cpu()) {
stop_this_cpu();
}
k8_init_and_stop_secondaries();
}
/* Setup the console */
pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);

16
src/mainboard/amd/serenade/auto.c
View File

@ -25,6 +25,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -163,20 +164,7 @@ static void main(unsigned long bist)
int needs_reset;
unsigned nodeid;
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
nodeid = lapicid() & 0xf;
/* Has this cpu already booted? */
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
if (!boot_cpu()) {
stop_this_cpu();
}
k8_init_and_stop_secondaries();
}
/* Setup the console */
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);

20
src/mainboard/amd/solo/auto.c
View File

@ -23,6 +23,7 @@
#include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
@ -111,24 +112,7 @@ static void main(unsigned long bist)
unsigned nodeid;
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
nodeid = lapicid() & 0xf;
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
if (!boot_cpu()) {
/* This LinuxBIOS image is built for UP only */
stop_this_cpu();
}
k8_init_and_stop_secondaries();
}
/* Setup the console */

24
src/mainboard/arima/hdama/auto.c
View File

@ -22,6 +22,7 @@
#include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
@ -135,7 +136,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
};
if (maxnodes > 2) {
print_debug("this mainboard is only designed for 2 cpus\r\n");
print_spew("this mainboard is only designed for 2 cpus\r\n");
maxnodes = 2;
}
@ -165,6 +166,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
static void main(unsigned long bist)
{
static const struct mem_controller cpu[] = {
@ -194,21 +197,7 @@ static void main(unsigned long bist)
int needs_reset;
if (bist == 0) {
unsigned nodeid;
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
nodeid = lapicid() & 0xf;
/* Has this cpu already booted? */
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
if (!boot_cpu()) {
stop_this_cpu();
}
k8_init_and_stop_secondaries();
}
/* Setup the console */
pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
@ -235,12 +224,13 @@ static void main(unsigned long bist)
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 0
dump_pci_devices();
#endif
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 2));
dump_pci_device(PCI_DEV(0, 0x18, 3));
#endif
#if 0

17
src/mainboard/ibm/e325/auto.c
View File

@ -25,6 +25,7 @@
#include "superio/NSC/pc87366/pc87366_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
@ -161,21 +162,7 @@ static void main(unsigned long bist)
unsigned nodeid;
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
nodeid = lapicid() & 0xf;
/* Has this cpu already booted? */
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
if (!boot_cpu()) {
stop_this_cpu();
}
k8_init_and_stop_secondaries();
}
/* Setup the console */
pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);

17
src/mainboard/ibm/e326/auto.c
View File

@ -25,6 +25,7 @@
#include "superio/NSC/pc87366/pc87366_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
@ -161,21 +162,7 @@ static void main(unsigned long bist)
unsigned nodeid;
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
nodeid = lapicid() & 0xf;
/* Has this cpu already booted? */
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
if (!boot_cpu()) {
stop_this_cpu();
}
k8_init_and_stop_secondaries();
}
/* Setup the console */
pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);

55
src/mainboard/island/aruma/auto.c
View File

@ -25,6 +25,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -128,31 +129,7 @@ static void main(unsigned long bist)
int needs_reset;
if (bist == 0) {
unsigned nodeid;
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
nodeid=lapicid() & 0xf;
#if ENABLE_APIC_EXT_ID == 1
enable_apic_ext_id(nodeid);
if(nodeid != 0) {
/* CPU apicid is from 0x10 */
lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID)
| (APIC_ID_OFFSET<<24) ) );
}
#endif
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
if (!boot_cpu()) {
stop_this_cpu();
}
k8_init_and_stop_secondaries();
}
/* Setup the console */
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
@ -173,20 +150,20 @@ static void main(unsigned long bist)
print_pci_devices();
#endif
#if (ALLOW_HT_OVERCLOCKING==1) && (USE_FALLBACK_IMAGE==0)
if(read_option(CMOS_VSTART_amdk8_1GHz, CMOS_VLEN_amdk8_1GHz, 0))
{
print_debug("AMDK8 allowed at 1GHz\r\n");
} else {
print_debug("AMDK8 allowed at 800Hz only\r\n");
}
if(read_option(CMOS_VSTART_amd8131_800MHz, CMOS_VLEN_amd8131_800MHz, 0))
{
print_debug("AMD8131 allowed at 800MHz\r\n");
} else {
print_debug("AMD8131 allowed at 600Hz only\r\n");
}
#endif
//#if (ALLOW_HT_OVERCLOCKING==1) && (USE_FALLBACK_IMAGE==0)
// if(read_option(CMOS_VSTART_amdk8_1GHz, CMOS_VLEN_amdk8_1GHz, 0))
// {
// print_debug("AMDK8 allowed at 1GHz\r\n");
// } else {
// print_debug("AMDK8 allowed at 800Hz only\r\n");
// }
// if(read_option(CMOS_VSTART_amd8131_800MHz, CMOS_VLEN_amd8131_800MHz, 0))
// {
// print_debug("AMD8131 allowed at 800MHz\r\n");
// } else {
// print_debug("AMD8131 allowed at 600Hz only\r\n");
// }
//#endif
if (needs_reset) {
print_info("HyperT reset -\r\n");
soft_reset();

17
src/mainboard/newisys/khepri/auto.c
View File

@ -23,6 +23,7 @@
#include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
@ -111,21 +112,7 @@ static void main(unsigned long bist)
unsigned nodeid;
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
nodeid = lapicid() & 0xf;
/* Has this cpu already booted? */
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
if (!boot_cpu()) {
stop_this_cpu();
}
k8_init_and_stop_secondaries();
}
/* Setup the console */
pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);

50
src/mainboard/tyan/s2875/auto.c
View File

@ -24,6 +24,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -112,11 +113,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "sdram/generic_sdram.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@ -149,47 +145,8 @@ static void main(unsigned long bist)
int needs_reset;
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
#endif
enable_lapic();
init_timer();
#if CONFIG_LOGICAL_CPUS==1
id = get_node_core_id_x();
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(id.nodeid);
// start_other_core(id.nodeid);
}
#else
nodeid = lapicid();
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
#endif
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
k8_init_and_stop_secondaries();
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
@ -202,9 +159,6 @@ static void main(unsigned long bist)
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
start_other_cores();
#endif
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) {
print_info("ht reset -\r\n");

45
src/mainboard/tyan/s2880/auto.c
View File

@ -24,6 +24,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -149,46 +150,8 @@ static void main(unsigned long bist)
};
int needs_reset;
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
#endif
enable_lapic();
init_timer();
#if CONFIG_LOGICAL_CPUS==1
id = get_node_core_id_x();
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(id.nodeid);
}
#else
nodeid = lapicid();
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
#endif
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
k8_init_and_stop_secondaries();
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
@ -201,10 +164,6 @@ static void main(unsigned long bist)
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
start_other_cores();
#endif
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) {
print_info("ht reset -\r\n");

43
src/mainboard/tyan/s2881/auto.c
View File

@ -24,6 +24,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -114,11 +115,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* tyan does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@ -156,39 +152,7 @@ static void main(unsigned long bist)
#endif
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
#endif
enable_lapic();
init_timer();
#if CONFIG_LOGICAL_CPUS==1
id = get_node_core_id_x();
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(id.nodeid);
}
#else
nodeid = lapicid();
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
#endif
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
k8_init_and_stop_secondaries();
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
@ -200,9 +164,6 @@ static void main(unsigned long bist)
setup_s2881_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
start_other_cores();
#endif
// automatically set that for you, but you might meet tight space
needs_reset |= ht_setup_chains_x();
if (needs_reset) {

45
src/mainboard/tyan/s2882/auto.c
View File

@ -24,6 +24,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -113,11 +114,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@ -160,40 +156,8 @@ static void main(unsigned long bist)
#endif
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
#endif
enable_lapic();
init_timer();
#if CONFIG_LOGICAL_CPUS==1
id = get_node_core_id_x();
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(id.nodeid);
}
#else
nodeid = lapicid();
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
#endif
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
}
k8_init_and_stop_secondaries();
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
@ -204,9 +168,6 @@ static void main(unsigned long bist)
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
start_other_cores();
#endif
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
print_info("ht reset -\r\n");

77
src/mainboard/tyan/s2885/auto.c
View File

@ -23,6 +23,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -121,13 +122,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* tyan does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#else
#include "cpu/amd/model_fxx/node_id.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@ -160,72 +154,9 @@ static void main(unsigned long bist)
};
int needs_reset;
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
id = get_node_core_id_x(); // that is initid
#if ENABLE_APIC_EXT_ID == 1
if(id.coreid == 0) {
enable_apic_ext_id(id.nodeid);
}
#endif
#else
nodeid = get_node_id();
#if ENABLE_APIC_EXT_ID == 1
enable_apic_ext_id(nodeid);
#endif
#endif
enable_lapic();
init_timer();
#if CONFIG_LOGICAL_CPUS==1
#if ENABLE_APIC_EXT_ID == 1
#if LIFT_BSP_APIC_ID == 0
if( id.nodeid != 0 ) //all except cores in node0
#endif
lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
#endif
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(id.nodeid);
}
#else
#if ENABLE_APIC_EXT_ID == 1
#if LIFT_BSP_APIC_ID == 0
if(nodeid != 0)
#endif
lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
#endif
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
#endif
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
k8_init_and_stop_secondaries();
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
@ -238,10 +169,6 @@ static void main(unsigned long bist)
setup_s2885_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
start_other_cores();
#endif
// automatically set that for you, but you might meet tight space
needs_reset |= ht_setup_chains_x();

53
src/mainboard/tyan/s2891/auto.c
View File

@ -26,6 +26,7 @@
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@ -77,11 +78,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* tyan does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@ -125,45 +121,10 @@ static void main(unsigned long bist)
#endif
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
#endif
enable_lapic();
init_timer();
#if CONFIG_LOGICAL_CPUS==1
id = get_node_core_id_x();
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(id.nodeid);
}
#else
nodeid = lapicid();
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
#endif
post_code(0x31);
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
k8_init_and_stop_secondaries();
}
post_code(0x32);
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
@ -175,12 +136,8 @@ static void main(unsigned long bist)
setup_s2891_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
needs_reset |= ht_setup_chains_x();
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();

54
src/mainboard/tyan/s2892/auto.c
View File

@ -26,6 +26,7 @@
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@ -76,11 +77,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* tyan does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@ -125,47 +121,9 @@ static void main(unsigned long bist)
};
int needs_reset;
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
#endif
enable_lapic();
init_timer();
#if CONFIG_LOGICAL_CPUS==1
id = get_node_core_id_x();
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(id.nodeid);
// start_other_core(id.nodeid);
}
#else
nodeid = lapicid();
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
#endif
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
k8_init_and_stop_secondaries();
}
@ -179,12 +137,8 @@ static void main(unsigned long bist)
setup_s2892_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
needs_reset |= ht_setup_chains_x();
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();

82
src/mainboard/tyan/s2895/auto.c
View File

@ -28,6 +28,7 @@
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
@ -106,12 +107,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* tyan does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#else
#include "cpu/amd/model_fxx/node_id.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
@ -163,79 +158,12 @@ static void main(unsigned long bist)
};
int needs_reset;
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
id = get_node_core_id_x(); // that is initid
#if ENABLE_APIC_EXT_ID == 1
if(id.coreid == 0) {
enable_apic_ext_id(id.nodeid);
}
#endif
#else
nodeid = get_node_id();
#if ENABLE_APIC_EXT_ID == 1
enable_apic_ext_id(nodeid);
#endif
#endif
enable_lapic();
init_timer();
post_code(0x30);
#if CONFIG_LOGICAL_CPUS==1
#if ENABLE_APIC_EXT_ID == 1
#if LIFT_BSP_APIC_ID == 0
if( id.nodeid != 0 ) //all except cores in node0
#endif
lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
#endif
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(id.nodeid);
}
#else
#if ENABLE_APIC_EXT_ID == 1
#if LIFT_BSP_APIC_ID == 0
if(nodeid != 0)
#endif
lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
#endif
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
#endif
post_code(0x31);
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
k8_init_and_stop_secondaries();
}
post_code(0x32);
// post_code(0x32);
lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
@ -249,10 +177,6 @@ static void main(unsigned long bist)
setup_s2895_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
needs_reset |= ht_setup_chains_x();

50
src/mainboard/tyan/s4880/auto.c
View File

@ -24,6 +24,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -125,11 +126,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* tyan does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
@ -202,47 +198,9 @@ static void main(unsigned long bist)
};
int i;
int needs_reset;
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
#endif
enable_lapic();
init_timer();
#if CONFIG_LOGICAL_CPUS==1
id = get_node_core_id_x();
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(id.nodeid);
// start_other_core(id.nodeid);
}
#else
nodeid = lapicid();
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
#endif
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
k8_init_and_stop_secondaries();
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
@ -256,10 +214,6 @@ static void main(unsigned long bist)
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
start_other_cores();
#endif
needs_reset |= ht_setup_chains_x();
if (needs_reset) {

74
src/mainboard/tyan/s4882/auto.c
View File

@ -23,6 +23,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "cpu/amd/dualcore/dualcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -129,13 +130,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* tyan does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#else
#include "cpu/amd/model_fxx/node_id.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
@ -208,68 +202,9 @@ static void main(unsigned long bist)
};
int i;
int needs_reset;
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
id = get_node_core_id_x(); // that is initid
#if ENABLE_APIC_EXT_ID == 1
if(id.coreid == 0) {
enable_apic_ext_id(id.nodeid);
}
#endif
#else
nodeid = get_node_id();
#if ENABLE_APIC_EXT_ID == 1
enable_apic_ext_id(nodeid);
#endif
#endif
enable_lapic();
init_timer();
#if CONFIG_LOGICAL_CPUS==1
#if ENABLE_APIC_EXT_ID == 1
#if LIFT_BSP_APIC_ID == 0
if( id.nodeid != 0 ) //all except cores in node0
#endif
lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
#endif
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(id.nodeid);
}
#else
#if ENABLE_APIC_EXT_ID == 1
#if LIFT_BSP_APIC_ID == 0
if(nodeid != 0)
#endif
lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
#endif
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
#endif
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
k8_init_and_stop_secondaries();
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
@ -283,11 +218,6 @@ static void main(unsigned long bist)
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
print_info("ht reset -\r\n");