amd/torpedo: Remove stale ssdt*.asl
They're not referenced in the code anywhere. Change-Id: I4805e11523ca7d3cffb484c719f479b7a6ba3e15 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10384 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Vladimir Serbinenko
parent
2cb2978559
commit
fde81099fa
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@ -1,83 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
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{
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Scope (_SB)
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{
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External (DADD, MethodObj)
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External (GHCE, MethodObj)
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External (GHCN, MethodObj)
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External (GHCL, MethodObj)
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External (GHCD, MethodObj)
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External (GNUS, MethodObj)
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External (GIOR, MethodObj)
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External (GMEM, MethodObj)
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External (GWBN, MethodObj)
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External (GBUS, MethodObj)
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External (PICF)
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External (\_SB.PCI0.LNKA, DeviceObj)
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External (\_SB.PCI0.LNKB, DeviceObj)
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External (\_SB.PCI0.LNKC, DeviceObj)
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External (\_SB.PCI0.LNKD, DeviceObj)
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Device (PCIX)
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{
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// BUS ? Second HT Chain
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Name (HCIN, 0xcc) // HC2 0x01
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Name (_UID, 0xdd) // HC 0x03
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Name (_HID, "PNP0A03")
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Method (_ADR, 0, NotSerialized) //Fake bus should be 0
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{
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Return (DADD(GHCN(HCIN), 0x00000000))
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}
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Method (_BBN, 0, NotSerialized)
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{
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Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
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}
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Method (_STA, 0, NotSerialized)
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{
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Return (\_SB.GHCE(HCIN))
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF0, ResourceTemplate () { })
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Store( GHCN(HCIN), Local4)
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Store( GHCL(HCIN), Local5)
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Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
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Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
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Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
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Return (Local3)
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}
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#include "acpi/pci2_hc.asl"
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}
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}
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}
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@ -1,83 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
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{
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Scope (_SB)
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{
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External (DADD, MethodObj)
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External (GHCE, MethodObj)
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External (GHCN, MethodObj)
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External (GHCL, MethodObj)
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External (GHCD, MethodObj)
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External (GNUS, MethodObj)
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External (GIOR, MethodObj)
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External (GMEM, MethodObj)
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External (GWBN, MethodObj)
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External (GBUS, MethodObj)
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External (PICF)
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External (\_SB.PCI0.LNKA, DeviceObj)
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External (\_SB.PCI0.LNKB, DeviceObj)
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External (\_SB.PCI0.LNKC, DeviceObj)
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External (\_SB.PCI0.LNKD, DeviceObj)
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Device (PCIX)
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{
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// BUS ? Second HT Chain
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Name (HCIN, 0xcc) // HC2 0x01
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Name (_UID, 0xdd) // HC 0x03
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Name (_HID, "PNP0A03")
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Method (_ADR, 0, NotSerialized) //Fake bus should be 0
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{
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Return (DADD(GHCN(HCIN), 0x00000000))
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}
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Method (_BBN, 0, NotSerialized)
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{
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Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
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}
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Method (_STA, 0, NotSerialized)
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{
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Return (\_SB.GHCE(HCIN))
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF0, ResourceTemplate () { })
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Store( GHCN(HCIN), Local4)
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Store( GHCL(HCIN), Local5)
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Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
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Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
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Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
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Return (Local3)
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}
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#include "acpi/pci3_hc.asl"
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}
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}
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}
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@ -1,83 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
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{
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Scope (_SB)
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{
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External (DADD, MethodObj)
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External (GHCE, MethodObj)
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External (GHCN, MethodObj)
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External (GHCL, MethodObj)
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External (GHCD, MethodObj)
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External (GNUS, MethodObj)
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External (GIOR, MethodObj)
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External (GMEM, MethodObj)
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External (GWBN, MethodObj)
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External (GBUS, MethodObj)
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External (PICF)
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External (\_SB.PCI0.LNKA, DeviceObj)
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External (\_SB.PCI0.LNKB, DeviceObj)
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External (\_SB.PCI0.LNKC, DeviceObj)
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External (\_SB.PCI0.LNKD, DeviceObj)
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Device (PCIX)
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{
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// BUS ? Second HT Chain
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Name (HCIN, 0xcc) // HC2 0x01
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Name (_UID, 0xdd) // HC 0x03
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Name (_HID, "PNP0A03")
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Method (_ADR, 0, NotSerialized) //Fake bus should be 0
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{
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Return (DADD(GHCN(HCIN), 0x00000000))
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}
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Method (_BBN, 0, NotSerialized)
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{
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Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
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}
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Method (_STA, 0, NotSerialized)
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{
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Return (\_SB.GHCE(HCIN))
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF0, ResourceTemplate () { })
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Store( GHCN(HCIN), Local4)
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Store( GHCL(HCIN), Local5)
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Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
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Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
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Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
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Return (Local3)
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}
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#include "acpi/pci4_hc.asl"
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}
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}
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}
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@ -1,84 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
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{
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Scope (_SB)
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{
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External (DADD, MethodObj)
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External (GHCE, MethodObj)
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External (GHCN, MethodObj)
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External (GHCL, MethodObj)
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External (GHCD, MethodObj)
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External (GNUS, MethodObj)
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External (GIOR, MethodObj)
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External (GMEM, MethodObj)
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External (GWBN, MethodObj)
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External (GBUS, MethodObj)
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External (PICF)
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External (\_SB.PCI0.LNKA, DeviceObj)
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External (\_SB.PCI0.LNKB, DeviceObj)
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External (\_SB.PCI0.LNKC, DeviceObj)
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External (\_SB.PCI0.LNKD, DeviceObj)
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Device (PCIX)
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{
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// BUS ? Second HT Chain
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Name (HCIN, 0xcc) // HC2 0x01
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Name (_UID, 0xdd) // HC 0x03
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Name (_HID, "PNP0A03")
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Method (_ADR, 0, NotSerialized) //Fake bus should be 0
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{
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Return (DADD(GHCN(HCIN), 0x00000000))
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}
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Method (_BBN, 0, NotSerialized)
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{
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Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
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}
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Method (_STA, 0, NotSerialized)
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{
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Return (\_SB.GHCE(HCIN))
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF0, ResourceTemplate () { })
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Store( GHCN(HCIN), Local4)
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Store( GHCL(HCIN), Local5)
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Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
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Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
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Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
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Return (Local3)
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}
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#include "acpi/pci5_hc.asl"
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}
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}
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}
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