northbridge/amd/amdht: Add comment for HT Freq write ordering

The BKDG is not correct regarding HT Freq write ordering;
indicate this in a comment to avoid confusion.

Change-Id: I37db191c144c81aba5d4a1e6291db5669a35a31a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12030
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/northbridge/amd/amdht/h3ncmn.c

@@ -1555,6 +1555,10 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb)
 			} else {
 				temp2 = 0x0;
 			}
+			/* NOTE
+			 * The Family 15h BKDG Rev. 3.14 is wrong
+			 * Freq[4] must be set before Freq[3:0], otherwise the register writes will be ignored!
+			 */
 			if (is_gt_rev_d())
 				AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG_2, 0, 0, &temp2);
 			AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG, 11, 8, &temp);