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soc/amd/picasso: Add data fabric read helper function 

Add new helper function to support reading a register from the data
fabric.

BUG=b:155307433
TEST=Boot trembyle with If64fd624597b2ced014ba7f0332a6a48143c0e8c and
confirm read values match expected values.
BRANCH=Zork

Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47726
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jason Glenesk 2020-11-02 19:56:49 -08:00 committed by Felix Held
parent 44f41537af
commit fe09a6fd47
2 changed files with 36 additions and 0 deletions
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20
src/soc/amd/picasso/data_fabric.c
View File

@ -167,3 +167,23 @@ static const struct pci_driver data_fabric_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_AMD,
.devices = pci_device_ids,
};
uint32_t data_fabric_read_reg32(uint8_t function, uint16_t reg, uint8_t instance_id)
{
uint32_t fabric_indirect_access_reg = 0;
if (instance_id == BROADCAST_FABRIC_ID)
/* No bit masking required. Macros will apply mask to values. */
return pci_read_config32(_SOC_DEV(DF_DEV, function), reg);
fabric_indirect_access_reg |= DF_IND_CFG_INST_ACC_EN;
/* Register offset field [10:2] in this register corresponds to [10:2] of the
requested offset. */
fabric_indirect_access_reg |= reg & DF_IND_CFG_ACC_REG_MASK;
fabric_indirect_access_reg |=
(function << DF_IND_CFG_ACC_FUN_SHIFT) & DF_IND_CFG_ACC_FUN_MASK;
fabric_indirect_access_reg |= instance_id << DF_IND_CFG_INST_ID_SHIFT;
pci_write_config32(SOC_DF_F4_DEV, DF_FICAA_BIOS, fabric_indirect_access_reg);
return pci_read_config32(SOC_DF_F4_DEV, DF_FICAD_LO);
}

16
src/soc/amd/picasso/include/soc/data_fabric.h
View File

@ -7,6 +7,7 @@
/* D18F0 - Fabric Configuration registers */
#define IOMS0_FABRIC_ID 9
#define BROADCAST_FABRIC_ID 0xff
#define D18F0_VGAEN 0x80
#define VGA_ADDR_ENABLE BIT(0)
@ -24,6 +25,21 @@
#define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0)
#define NB_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0)
#define DF_FICAA_BIOS 0x5C
#define DF_FICAD_LO 0x98
#define DF_FICAD_HI 0x9C
#define DF_IND_CFG_INST_ACC_EN (1 << 0)
#define DF_IND_CFG_ACC_REG_SHIFT 2
#define DF_IND_CFG_ACC_REG_MASK (0x1ff << DF_IND_CFG_ACC_REG_SHIFT)
#define DF_IND_CFG_ACC_FUN_SHIFT 11
#define DF_IND_CFG_ACC_FUN_MASK (0x7 << DF_IND_CFG_ACC_REG_SHIFT)
#define DF_IND_CFG_64B_EN_SHIFT 14
#define DF_IND_CFG_64B_EN (0x1 << DF_IND_CFG_ACC_REG_SHIFT)
#define DF_IND_CFG_INST_ID_SHIFT 16
#define DF_IND_CFG_INST_ID_MASK (0xff << DF_IND_CFG_ACC_REG_SHIFT)
void data_fabric_set_mmio_np(void);
uint32_t data_fabric_read_reg32(uint8_t function, uint16_t reg, uint8_t instance_id);
#endif /* AMD_PICASSO_DATA_FABRIC_H */