From fe234c4d2a6ce0e1279597566336fe9277b8aa3b Mon Sep 17 00:00:00 2001 From: zbao Date: Thu, 2 Jul 2015 16:53:09 -0400 Subject: [PATCH] AMD Merlin Falcon: Mask bit 31 of BIST while doing BIST check This is a result of the Silcon Observation. On warm reset, the BIST is 0x80000000, which causes BIST error. We skip checking this bit. The update will be in CZ BKDG 1.05. The code is tested on AMD/bettong. Change-Id: I51c3f3567f758766079f7c8789f1ff072e1a7c53 Signed-off-by: Zheng Bao Signed-off-by: Zheng Bao Reviewed-on: http://review.coreboot.org/10902 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/mainboard/amd/bettong/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 10813b3534..a8a2777a79 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -48,7 +48,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ post_code(0x34); - report_bist_failure(bist); + report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */ /* Load MPB */ val = cpuid_eax(1);