mb/google/drallion/variants/drallion: Set PCH Thermal Trip point to 77°C
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Drallion. Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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@ -175,6 +175,9 @@ chip soc/intel/cannonlake
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register "tcc_offset" = "1"
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register "tcc_offset" = "1"
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# PCH Thermal Trip Temperature in deg C
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register "common_soc_config.pch_thermal_trip" = "77"
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register "common_soc_config" = "{
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.i2c[0] = {
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.i2c[0] = {
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