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mb/google/drallion/variants/drallion: Set PCH Thermal Trip point to 77°C 

PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.

BUG=None
BRANCH=None
TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Drallion.

Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This commit is contained in:
Sumeet Pawnikar 2020-03-09 12:56:30 +05:30 committed by Patrick Georgi
parent 6bc471461b
commit fe2a4c1001
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/google/drallion/variants/drallion/devicetree.cb
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@ -175,6 +175,9 @@ chip soc/intel/cannonlake
register "tcc_offset" = "1" register "tcc_offset" = "1"
# PCH Thermal Trip Temperature in deg C
register "common_soc_config.pch_thermal_trip" = "77"
register "common_soc_config" = "{ register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = { .i2c[0] = {