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mb/starlabs/starbook/adl: Enable ASPM 

Enable ASPM for RP5 (wireless) and RP9 (SSD).

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I428040caf171bdcfedc285cdeddc55bcbec40f3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72753
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2023-02-02 15:53:03 +00:00 committed by Felix Held
parent ab4ace2b8c
commit fe2f50f496
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
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@ -100,6 +100,8 @@ chip soc/intel/alderlake
.clk_src = 2, .clk_src = 2,
.clk_req = 2, .clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_LTR | PCIE_RP_AER,
.PcieRpL1Substates = L1_SS_L1_2,
.pcie_rp_aspm = ASPM_L0S_L1,
}" }"
smbios_slot_desc "SlotTypePciExpressGen3X1" smbios_slot_desc "SlotTypePciExpressGen3X1"
"SlotLengthShort" "SlotLengthShort"
@ -117,6 +119,9 @@ chip soc/intel/alderlake
.clk_src = 1, .clk_src = 1,
.clk_req = 1, .clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_LTR | PCIE_RP_AER,
.PcieRpL1Substates = L1_SS_L1_2,
.pcie_rp_aspm = ASPM_L0S_L1,
}" }"
smbios_slot_desc "SlotTypeM2Socket3" smbios_slot_desc "SlotTypeM2Socket3"
"SlotLengthLong" "SlotLengthLong"